公开(公告)号：US06436824B1

公开(公告)日：2002-08-20

申请号：US09346526

申请日：1999-07-02

申请人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

发明人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

IPC分类号： H01L2144

CPC分类号： H01L21/02211 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/3125 ,  H01L21/314 ,  H01L21/76807

摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

摘要翻译： 提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。 通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。 此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。 通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。 或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。 此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。

公开(公告)号：US06376353B1

公开(公告)日：2002-04-23

申请号：US09609167

申请日：2000-07-03

申请人： Mei Sheng Zhou ,  Sangki Hong ,  Simon Chooi

发明人： Mei Sheng Zhou ,  Sangki Hong ,  Simon Chooi

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/7684 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/00013

摘要： Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al—Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al—Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al—Cu bond layer or region is placed on top of the underlying copper pad metal. This Al—Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.

摘要翻译： 本发明公开了用于在纯铜镶嵌件上制造引线接合焊盘的改进方法。 本发明涉及用于半导体集成电路器件的各种制造方法，更具体地涉及形成Al-Cu合金顶部焊盘金属层，其改善了引线接合，顶部Al-Cu和下面的铜焊盘之间的粘附 冶金。 本发明描述了其中特殊的Al-Cu键合层或区域放置在下面的铜垫金属的顶部上的工艺。 纯铜上的这种Al-Cu键合焊盘（其间具有阻挡层）提供了改善的与焊盘焊接粘合的线粘合，并且防止了焊线粘附试验期间的剥离。

公开(公告)号：US06368958B2

公开(公告)日：2002-04-09

申请号：US09876598

申请日：2001-06-08

申请人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

发明人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C18/1608 ,  C25D7/123 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877

摘要： A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer. The copper layer may comprise a thin seed layer for use in subsequent electroplating or electroless plating of copper or may comprise a thick copper layer to fill the vias and trenches. The integrated circuit is completed.

摘要翻译： 已经实现了在制造集成电路器件中使用Cu（I）离子从由极性有机溶剂稳定的溶液中进行歧化的单层和双镶嵌互连的沉积铜层的新方法。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化电介质层以形成用于计划的双镶嵌互连的通孔和沟槽。 沉积覆盖在介电层上的阻挡层以对通孔和沟槽进行排列。 将由极性有机溶剂稳定的简单的Cu（I）离子溶液涂覆在所述阻挡层上。 向稳定化的简单的Cu（I）离子溶液中加入水以引起Cu（I）离子溶液中简单的Cu（I）离子的歧化。 沉积在屏障层上的铜层。 铜层可以包括用于铜的后续电镀或无电镀的薄种子层，或者可以包括用于填充通孔和沟槽的厚铜层。 集成电路完成。

公开(公告)号：US06340608B1

公开(公告)日：2002-01-22

申请号：US09612564

申请日：2000-07-07

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Ho ,  Xu Yi

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Ho ,  Xu Yi

IPC分类号： H01L2150

CPC分类号： H01L24/81 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.

摘要翻译： 提供了具有暴露的金属端接垫的半导体芯片，以及具有其上相应的暴露的金属轨道的单独的基板。 在暴露的金属端接垫上方形成金属凸块。 在金属凸块上形成感光树脂插头。 半导体芯片的金属凸块与分离的基板上的对应金属轨迹对准。 金属凸块上的感光树脂插头与相应的金属轨道配合。 感光树脂插头暴露于紫外线光以固化光敏树脂插头，将半导体芯片的金属凸块永久地连接到单独基板的相应金属轨道上。

公开(公告)号：US06271115B1

公开(公告)日：2001-08-07

申请号：US09604065

申请日：2000-06-26

申请人： Wen Jun Liu ,  Simon Chooi ,  Mei Sheng Zhou ,  Raymond Joy

发明人： Wen Jun Liu ,  Simon Chooi ,  Mei Sheng Zhou ,  Raymond Joy

IPC分类号： H01L214763

CPC分类号： H01L21/02071

摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O2 and H2O; the second step is in a microwave generated plasma containing O2 and N2; the third step is in a microwave generated plasma containing H2O; the fourth step is in a microwave generated plasma containing O2 and N2; and the fifth step is in a microwave generated plasma containing H2O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.

摘要翻译： 已经开发了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。 该方法是五步法，其中第一步是在微波产生的含有O 2和H 2 O的等离子体中; 第二步是在微波产生的含有O2和N2的等离子体中; 第三步是在微波产生的含有H 2 O的等离子体中; 第四步是在微波产生的含有O2和N2的等离子体中; 并且第五步是在含有H 2 O的微波产生的等离子体中。 在同时开始钝化过程的同时开始除去光致抗蚀剂的第一步骤在蚀刻含氯蚀刻剂中的铝或铝 - 铜层之后会导致残留物去除光致抗蚀剂。

公开(公告)号：US06261942B1

公开(公告)日：2001-07-17

申请号：US09490156

申请日：2000-01-24

申请人： Mei Sheng Zhou ,  Simon Chooi ,  Xu Yi

发明人： Mei Sheng Zhou ,  Simon Chooi ,  Xu Yi

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  H01L21/312 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.

摘要翻译： 一种在微电子制造中将空气引入相邻导电结构之间的间隙中以减少它们之间的电容耦合的方法。 图案化的金属层沉积在基底上。 该层衬有CVD氧化物。 一次性间隙填充材料沉积在衬里的金属层上。 通过在CVD氧化物层上沉积TiN层，在间隙填充上形成两层“空气桥”。 这种结构通过几种化学方法使其多孔化。 氧气等离子体通过多孔空气桥与其下方的间隙填充反应并溶解。 反应产物通过多孔气桥逸出，导致空气填充的间隙。

公开(公告)号：US06228713B1

公开(公告)日：2001-05-08

申请号：US09342035

申请日：1999-06-28

申请人： Yelehanka Ramachandramurthy Pradeep ,  Vijay Kumar Chhagan ,  Jie Yu ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Vijay Kumar Chhagan ,  Jie Yu ,  Mei Sheng Zhou

IPC分类号： H01H21336

CPC分类号： H01L27/11521 ,  H01L21/76224

摘要： A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.

摘要翻译： 一种在存储器件中制作自对准浮动栅极的方法。 该方法使用用于浅沟槽隔离（STI）的沟槽蚀刻对浮栅（FG）进行图案化。 因为浮动栅极（FG）与凸起的STI相邻，所以在FG和CG之间消除了尖角，从而增加了栅间电介质层的有效性。 该方法包括：在衬底上形成第一介质层（栅极氧化物）和多晶硅层，蚀刻通过第一电介质氧化物层和多晶硅层并进入衬底以形成沟槽。 剩余的第一电介质层和多晶硅层用作隧道电介质层和浮栅。 沟槽填充有隔离层。 去除掩模层。 在浮栅和隔离层上形成隔间电介质层和控制栅极。

公开(公告)号：US6156598A

公开(公告)日：2000-12-05

申请号：US460113

申请日：1999-12-13

申请人： Mei Sheng Zhou ,  Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Ying Keung Leung

发明人： Mei Sheng Zhou ,  Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Ying Keung Leung

IPC分类号： H01L21/265 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66598 ,  H01L21/2652 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659

摘要： A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyond the L-shaped spacer. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiments, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer. Impurity ions are implanted into the surface of the semiconductor structure forming lightly doped source and drain extensions where the ions are implanted through the L-shaped spacer, and forming source and drain regions beyond the L-shaped spacer where the ions are implanted without passing through the L-shaped spacer.

摘要翻译： 使用牺牲有机顶涂层形成L形间隔物的方法，然后使用L形间隔物同时将轻掺杂的源极和漏极延伸部注入L型间隔物，同时将源极和漏极区域注入超过L形间隔物 。 提供其上具有栅极结构的半导体结构。 在栅极结构上形成衬里氧化物层。 介电间隔层形成在衬垫氧化物层上。 在优选实施例中，电介质间隔层包括氮化硅层或氮氧化硅层。 在电介质间隔层上形成牺牲有机层。 牺牲有机层和电介质间隔层被各向异性蚀刻以形成包括三角形牺牲有机结构和L形介电间隔物的间隔物。 去除三角形牺牲有机结构留下L形介电隔离物。 将杂质离子注入到形成轻掺杂源极和漏极延伸部分的半导体结构的表面中，其中离子通过L形间隔物注入，并且形成超过L形间隔物的源极和漏极区域，其中离子被注入而不通过 L形间隔物。

公开(公告)号：US5930627A

公开(公告)日：1999-07-27

申请号：US851403

申请日：1997-05-05

申请人： Mei Sheng Zhou ,  Sheau-Tan Loong ,  Koon Lay Denise Tan ,  Jian Xun Li ,  Wing Hong Chiu ,  Kok Hiang Stephanie Tang

发明人： Mei Sheng Zhou ,  Sheau-Tan Loong ,  Koon Lay Denise Tan ,  Jian Xun Li ,  Wing Hong Chiu ,  Kok Hiang Stephanie Tang

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost.

摘要翻译： 富含硅的氮氧化硅被用作独立的蚀刻停止层以及作为多晶硅栅极电极上的覆盖层和侧壁部件的应用，以便防止由错配对接触掩模引起的绝缘体变薄和短路。 在一个实施例中，将富硅氧氮化硅层放置在具有常规侧壁和绝缘帽的多晶硅栅极上。 在另一个实施例中，绝缘帽和侧壁由富硅硅氮化硅形成。 如果由于不对准的接触掩模而被接合，则由富硅氧氮化物抑制随后沉积的绝缘层中的接触开口的蚀刻。 在另一个实施例中，在自对准源（SAS）区域的蚀刻期间，存储器件的多晶硅堆叠边缘被保形氮氧化硅层保护。 这些实施例以过程复杂性或成本的最小和几乎可忽略的增加来实现。

公开(公告)号：US5792708A

公开(公告)日：1998-08-11

申请号：US611585

申请日：1996-03-06

申请人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

发明人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

IPC分类号： H01L21/3213 ,  H01L21/08

CPC分类号： H01L21/32137

摘要： A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer. The anisotropic first etch process is a Reactive Ion Etch (RIE) anisotropic first etch process which simultaneously passivates the exposed sidewall edges of the patterned polysilicon layer. Finally, the polysilicon residues formed at the lower step level of the high step height patterned substrate layer are removed through an isotropic second etch process. The isotropic second etch process is a Reactive Ion Etch (RIE) isotropic second etch process which employs hydrogen bromide (HBr) and sulfur hexafluoride (SF6) as the reactant gases.

摘要翻译： 一种用于在高台阶高度图案化衬底层上形成无残留图案化多晶硅层的方法。 首先，提供在其上形成有高台阶高度图案化基板层的半导体基板。 形成在高台阶高度图案化衬底层上的是多晶硅层，并且在多晶硅层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层在高阶高度图案化衬底层的较低台阶处暴露多晶硅层的部分。 然后通过图案化的光致抗蚀剂层将多晶硅层图案化为使用各向异性第一蚀刻工艺的蚀刻掩模，以在高阶高度图案化衬底层的表面上产生图案化多晶硅层，并在高级步骤的较低级别处产生多晶硅残余物 高度图案化衬底层。 各向异性第一蚀刻工艺是反应离子蚀刻（RIE）各向异性第一蚀刻工艺，其同时钝化图案化多晶硅层的暴露的侧壁边缘。 最后，通过各向同性的第二蚀刻工艺去除在高阶高度图案化衬底层的较低台阶处形成的多晶硅残余物。 各向同性第二蚀刻工艺是使用溴化氢（HBr）和六氟化硫（SF6）作为反应气体的反应离子蚀刻（RIE）各向同性第二蚀刻工艺。