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    Non-volatile memory bank and page buffer therefor
    82.
    发明授权
    Non-volatile memory bank and page buffer therefor 有权
    非易失性存储器和页缓冲器

    公开(公告)号：US08879351B2

    公开(公告)日：2014-11-04

    申请号：US13618022

    申请日：2012-09-14

    Applicant: Jin-Ki Kim

    Inventor： Jin-Ki Kim

    IPC: G11C8/00 ,  G11C7/10 ,  G11C5/02 ,  G11C7/12 ,  G11C16/24 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/107 ,  G11C2216/14 ,  G11C2216/20 ,  G11C2216/30

    Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. Each half of the memory bank is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

    Abstract translation: 一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。 记忆库的每一半分为上部和下部。 每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。 存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。 具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据路径核心减少了芯片面积。 因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

    Circuit for clamping current in a charge pump
    83.
    发明授权
    Circuit for clamping current in a charge pump 有权
    用于在电荷泵中夹紧电流的电路

    公开(公告)号：US08860480B2

    公开(公告)日：2014-10-14

    申请号：US13873503

    申请日：2013-04-30

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Peter Vlasenko ,  Huy Tuong Mai

    IPC: H03L7/06 ,  H02M3/07 ,  H03K5/08 ,  H02M1/34 ,  H03L7/089 ,  G05F3/02

    CPC classification number: H02M3/07 ,  G05F1/625 ,  G05F3/02 ,  H02M1/34 ,  H02M3/073 ,  H03K5/086 ,  H03L7/0895

    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

    Abstract translation: 公开了一种用于钳位电荷泵中的电流的电路。 电荷泵包括具有多个开关电路晶体管的开关电路。 电路中的第一和第二对晶体管中的每一个可以在该晶体管截止期间从其相关联的一个开关电路晶体管提供电流的附加路径，使得来自开关电路晶体管的电流尖峰仅部分地透过 在开关电路晶体管和电荷泵的电容器之间延伸的路径。

    Partial block erase architecture for flash memory
    84.
    发明授权
    Partial block erase architecture for flash memory 有权
    闪存的部分块擦除架构

    公开(公告)号：US08842472B2

    公开(公告)日：2014-09-23

    申请号：US12785099

    申请日：2010-05-21

    Applicant: Jin-Ki Kim

    Inventor： Jin-Ki Kim

    IPC: G11C16/06 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/344 ,  G11C16/349

    Abstract: A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

    Abstract translation: 一种用于通过选择性地擦除存储器块的子块来增加闪存器件的寿命的方法和系统。 闪速存储器件的每个物理存储器块可被分割成至少两个逻辑子块，其中至少两个逻辑子块中的每个逻辑子块是可擦除的。 因此，只有逻辑子块的数据被擦除并重新编程，而另一个逻辑子块中的未修改数据避免了不必要的编程/擦除周期。 要擦除的逻辑子块可在块内的大小和位置上动态配置。 磨损均衡算法用于在存储器阵列的整个物理和逻辑子块中分布数据，以在编程和数据修改操作期间最大化物理块的寿命。

    Configurable module and memory subsystem
    87.
    发明授权
    Configurable module and memory subsystem 有权
    可配置模块和内存子系统

    公开(公告)号：US08767430B2

    公开(公告)日：2014-07-01

    申请号：US13957713

    申请日：2013-08-02

    Applicant: MOSAID Technologies Incorporated

    Inventor： Peter Gillingham ,  Roland Schuetz

    IPC: G11C5/02 ,  G11C5/00 ,  G11C5/06 ,  G11C8/00

    CPC classification number: G11C5/025 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4243 ,  G11C16/04

    Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

    Abstract translation: 可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。 每个MCD对具有与第二MCD通信的第一MCD。 每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。 响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。 环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

    METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES
    89.
    发明申请
    METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES 有权
    在集成电路设备中共享内部电源的方法和装置

    公开(公告)号：US20140119136A1

    公开(公告)日：2014-05-01

    申请号：US14148336

    申请日：2014-01-06

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Peter GILLINGHAM

    IPC: G11C5/14

    CPC classification number: G11C5/147 ,  G11C5/145 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  H01L24/04 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13009 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1434 ,  Y10T29/49117 ,  H01L2924/00

    Abstract: A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit 200 including multiple integrated circuits 202-205 each having internal power supplies is contained in an enclosure 201. Integrated circuits 202-205 are described showing how to make external connection to internal power supplies. Connections 208-212 are provided to the internal power supplies of each of devices 202-205. Another embodiment 500 of the system provides for disablement of regulators in multiple integrated circuits 502, 503, and 504 by another integrated circuit 501 for power consumption reduction. The method FIG. 6 includes providing devices and connecting the internal power supplies together. An integrated circuit 501 with a power supply 400 adapted to the system and method with additional circuitry 308, 404 and 402 for disabling a regulator 306 is described.

    Abstract translation: 描述了用于在集成电路设备中共享内部电源的方法，系统和装置。 包含多个具有内部电源的集成电路202-205的多器件集成电路200包含在外壳201中。描述了如何进行与内部电源的外部连接的集成电路202-205。 连接208-212被提供给每个设备202-205的内部电源。 该系统的另一个实施例500提供了另一个集成电路501对多个集成电路502,503和504中的稳压器的禁用，以降低功耗。 方法 6包括提供设备并将内部电源连接在一起。 描述了具有适用于具有用于禁用调节器306的附加电路308,404和402的系统和方法的电源400的集成电路501。

    Flash memory system
    90.
    发明授权
    Flash memory system 有权

    公开(公告)号：US11150808B2

    公开(公告)日：2021-10-19

    申请号：US16891402

    申请日：2020-06-03

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki Kim

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

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