公开(公告)号：US11894309B2

公开(公告)日：2024-02-06

申请号：US17121140

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tzuan-Horng Liu ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

公开(公告)号：US20240038740A1

公开(公告)日：2024-02-01

申请号：US18329530

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyundong Lee ,  Youngmin Kim ,  Joonseok Oh ,  Sangyun Lee ,  Changbo Lee

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/3107 ,  H01L24/16 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15174

Abstract: A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged around the semiconductor chip.

公开(公告)号：US20240038682A1

公开(公告)日：2024-02-01

申请号：US17814997

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tien-Chung YANG ,  Li-Hsien HUANG ,  Ming-Feng WU ,  Yung-Sheng LIU ,  Chun-Jen CHEN ,  Jun HE

IPC: H01L23/00 ,  H01L25/10 ,  H01L21/78 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L25/105 ,  H01L21/78 ,  H01L24/97 ,  H01L21/561 ,  H01L22/12 ,  H01L23/49811 ,  H01L23/3128

Abstract: A laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. In addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. The second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. Accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.

公开(公告)号：US20240038642A1

公开(公告)日：2024-02-01

申请号：US18121429

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Kim ,  Joonsung KIM ,  Hyeonseok LEE ,  Hyeonjeong HWANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.

公开(公告)号：US20240038549A1

公开(公告)日：2024-02-01

申请号：US18125958

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jakyoung GU ,  Minsoo KIM ,  Jihye SHIM ,  Kyoungok JUNG

IPC: H01L21/48 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L25/105 ,  H10B80/00 ,  H01L2225/1035 ,  H01L24/16

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of conductive patterns on a substrate, forming a photoresist film over the substrate to cover the plurality of conductive patterns, forming a photoresist pattern from the photoresist film by a photolithography process using a photomask that includes a transparent area, a light-shielding area, and a semi-transparent area transmitting only a portion of light incident thereon, wherein the photoresist pattern includes a via hole, which exposes one conductive pattern, and a recessed portion, which has a lower surface exposing a portion of the photoresist pattern, forming a conductive post in the via hole, and removing the photoresist pattern by using a photoresist stripping composition.

公开(公告)号：US11881472B2

公开(公告)日：2024-01-23

申请号：US17863695

申请日：2022-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin Park ,  Sunghawn Bae ,  Won Choi

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/48108 ,  H01L2224/48157 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

公开(公告)号：US11876029B2

公开(公告)日：2024-01-16

申请号：US17395574

申请日：2021-08-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takashi Iwamoto

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/315 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/49822 ,  H01L23/49844 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/24137 ,  H01L2224/24145

Abstract: A method of manufacturing an electronic component module includes a sacrificial-body arrangement step of disposing a sacrificial body on a first principal surface of a support, the support including the first principal surface and a second principal surface, the sacrificial body being smaller than the first principal surface when viewed in a thickness direction of the support, a resin molding step of molding a resin structure on the first principal surface so as to cover the sacrificial body disposed on the first principal surface, a recess forming step of forming a recess in the resin structure by removing the sacrificial body, a wiring-layer forming step of forming a wiring layer on a side surface of the recess and on a principal surface of the resin structure, the principal surface connecting with the side surface, and a component mounting step of mounting an electronic component in the recess.

公开(公告)号：US20240014192A1

公开(公告)日：2024-01-11

申请号：US18474168

申请日：2023-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/11 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/117 ,  H01L25/50 ,  H01L25/105 ,  H01L21/6835 ,  H01L21/02354 ,  H01L21/76883 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L25/0657 ,  H01L23/562 ,  H01L2224/32013 ,  H01L2224/1308 ,  H01L2224/83005 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68359 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83102 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L22/14

Abstract: A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

公开(公告)号：US20240006387A1

公开(公告)日：2024-01-04

申请号：US17856372

申请日：2022-07-01

Applicant: GM Cruise Holdings LLC

Inventor： Ajith Sreenilayam

IPC: H01L25/10 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L25/105 ,  H05K1/181 ,  H01L24/16 ,  H05K2201/10734 ,  H05K2201/10159 ,  B60W60/001

Abstract: The subject technology is related to autonomous vehicles (AV) and, in particular, to an autonomous driver system controller (ADSC) that is fixed to the AV. The AV comprises an electronic drivetrain configured to move the AV; and an autonomous driver system controller (ADSC) fixed to an interior surface of the AV and configured to control the electronic drivetrain with a processor connected to a plurality of memory integrated circuits (IC) that are fixed to a printed circuit board (PCB). The plurality of memory ICs are mounted on each side of the PCB using a ball grid array (BGA) with a column of pins in the BGA of a top-surface memory IC is longitudinally aligned with a corresponding column of pins in the BGA of a bottom-surface memory IC.

公开(公告)号：US20240006367A1

公开(公告)日：2024-01-04

申请号：US18361196

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu JENG ,  Shuo-Mao CHEN ,  Feng-Cheng HSU

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/25 ,  H01L25/0655 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/3128 ,  H01L2224/215 ,  H01L23/29

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and adjacent to the first chip. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a first molding layer over the first surface and surrounding the first chip. The chip package structure includes a second molding layer over the second surface and surrounding the second chip.