公开(公告)号：US20240105604A1

公开(公告)日：2024-03-28

申请号：US18526208

申请日：2023-12-01

申请人： Samsung Electronics Co., Ltd.

发明人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC分类号： H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US11937424B2

公开(公告)日：2024-03-19

申请号：US17458029

申请日：2021-08-26

申请人： SUNRISE MEMORY CORPORATION

发明人： Scott Brad Herner ,  Eli Harari

IPC分类号： H10B43/20

CPC分类号： H10B43/20

摘要： A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.

公开(公告)号：US11925026B2

公开(公告)日：2024-03-05

申请号：US17340371

申请日：2021-06-07

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H10B43/40 ,  G11C5/06 ,  H01L23/48 ,  H01L23/535 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/30

CPC分类号： H10B43/40 ,  G11C5/063 ,  H01L23/481 ,  H01L23/535 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/30

摘要： Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

公开(公告)号：US11889698B2

公开(公告)日：2024-01-30

申请号：US17190348

申请日：2021-03-02

申请人： KIOXIA CORPORATION

发明人： Yasuhito Yoshimizu ,  Hiroshi Nakaki ,  Kazuaki Nakajima

IPC分类号： H10B43/35 ,  H01L23/00 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20

CPC分类号： H10B43/35 ,  H01L24/46 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20

摘要： A semiconductor storage device includes first wiring layers stacked along a first direction, a first pillar including a first semiconductor layer and extending along the first direction through the first wiring layers, a second wiring layer disposed above the first pillar in the first direction and extending along a second direction perpendicular to the first direction, a semiconductor-containing layer including a first portion disposed on an upper end of the first pillar in the first direction, a second portion contacting the first portion and formed along the second wiring layer, and a third portion contacting an upper end of the second portion and extending along a third direction perpendicular to the first direction and crossing the second direction, and a first insulating layer between each of the first and second portions of the semiconductor-containing layer and the second wiring layer. An upper surface of the third portion contains a metal.

公开(公告)号：US11882699B2

公开(公告)日：2024-01-23

申请号：US17224100

申请日：2021-04-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC分类号： H10B43/20 ,  H01L29/78 ,  H01L29/66 ,  H10B41/20

CPC分类号： H10B43/20 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/20

摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20240008280A1

公开(公告)日：2024-01-04

申请号：US18346473

申请日：2023-07-03

申请人： Kioxia Corporation

发明人： Go OIKE

IPC分类号： H10B43/40 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B53/20

CPC分类号： H10B43/40 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/0688 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B53/20 ,  H01L23/53228

摘要： A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

公开(公告)号：US11864390B2

公开(公告)日：2024-01-02

申请号：US17017721

申请日：2020-09-11

申请人： Kioxia Corporation

发明人： Jumpei Sato

IPC分类号： H01L27/11573 ,  H10B43/40 ,  G11C16/08 ,  G11C16/30 ,  G11C16/24 ,  H10B43/20 ,  H10B43/35

CPC分类号： H10B43/40 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H10B43/20 ,  H10B43/35

摘要： According to one embodiment, a semiconductor memory device includes the following structure. A memory array is provided on a first-direction side of a substrate. The first direction intersects the substrate. The first peripheral circuit is provided between the substrate and the memory array. The second peripheral circuit is provided between the substrate and the memory array and on a second-direction side of the first peripheral circuit. The second direction intersects the first direction. The sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits. A second-direction length of the second peripheral circuit is smaller than half a second-direction length of the sense amplifier.

公开(公告)号：US11864367B2

公开(公告)日：2024-01-02

申请号：US17228496

申请日：2021-04-12

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Weihua Cheng ,  Jun Liu

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  G11C14/00 ,  G11C16/04 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06 ,  H01L29/04 ,  H01L29/16 ,  H01L21/76 ,  H10B12/00 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： H10B10/12 ,  G11C14/0018 ,  G11C16/0483 ,  H01L21/02013 ,  H01L21/2007 ,  H01L21/50 ,  H01L21/76 ,  H01L21/8221 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/04 ,  H01L29/16 ,  H10B12/02 ,  H10B12/033 ,  H10B12/05 ,  H10B12/09 ,  H10B12/31 ,  H10B12/50 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/08145 ,  H01L2224/291 ,  H01L2224/32145 ,  H01L2224/73215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896

摘要： First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US20230420283A1

公开(公告)日：2023-12-28

申请号：US18241990

申请日：2023-09-04

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L2924/13062 ,  H01L23/3677

摘要： A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, first transistors control power delivery to some second transistors; and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

公开(公告)号：US11856779B2

公开(公告)日：2023-12-26

申请号：US17853922

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Chih Lai ,  Chung-Te Lin

IPC分类号： H10B43/35 ,  H01L23/522 ,  H10B43/10 ,  H10B43/20

CPC分类号： H10B43/35 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/20 ,  H01L2924/145 ,  H01L2924/1438

摘要： A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.