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    Manufacturing method for a semiconductor device with reduced local current
    1.
    发明申请
    Manufacturing method for a semiconductor device with reduced local current 有权
    具有局部电流降低的半导体器件的制造方法

    公开(公告)号：US20040178459A1

    公开(公告)日：2004-09-16

    申请号：US10809011

    申请日：2004-03-25

    申请人： Sanyo Electric Co., Ltd., a Osaka, Japan corporation

    发明人： Eiji Nishibe ,  Shuichi Kikuchi

    IPC分类号： H01L027/01

    CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66674 ,  H01L29/7801

    摘要： A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.

    摘要翻译： 一种半导体器件，包括：第一栅极绝缘膜，其在P型半导体衬底内的N型阱区上图案形成; 第二栅极绝缘膜，形成在除了该第一栅极绝缘膜之外的半导体基板上; 栅极电极，其形成为使得该栅极桥接在第一栅极绝缘膜和第二栅极绝缘膜上; P型体区，其形成为使得该P型体区域位于与栅电极相邻的位置; N型源区和沟道区，形成在该P型体区内; 以及形成在与P型体区域分离的位置的N型漏极区域。

    Semiconductor device
    3.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20050056898A1

    公开(公告)日：2005-03-17

    申请号：US10969625

    申请日：2004-10-20

    申请人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

    发明人： Satoru Kaneko ,  Toshiyuki Ohkoda ,  Takao Myono

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H03K19/0185 ,  H01L29/76

    CPC分类号： H01L21/823892 ,  H01L21/8249 ,  H01L27/0222 ,  H01L27/0623 ,  H01L27/0921

    摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

    摘要翻译： 提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。 在P型单晶硅衬底上形成N型外延硅层，在N型外延硅层中形成P型阱区。 形成邻接在P型阱区的底部的P +型掩埋层和与P +型掩埋层部分重叠并将P型阱区与单晶硅衬底电隔离的N +型掩埋层 。 然后，在P型阱区域中形成MOS晶体管。

    Semiconductor device and method of manufacturing it
    4.
    发明申请
    Semiconductor device and method of manufacturing it 有权
    半导体装置及其制造方法

    公开(公告)号：US20040051125A1

    公开(公告)日：2004-03-18

    申请号：US10651855

    申请日：2003-08-29

    申请人： Sanyo Electric Co., Ltd., a Osaka, Japan corporation

    发明人： Shuichi Kikuchi ,  Eiji Nishibe

    IPC分类号： H01L021/336 ,  H01L029/76 ,  H01L031/062

    CPC分类号： H01L29/66659 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42368 ,  H01L29/7835

    摘要： To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.

    摘要翻译： 为了在确保耐电压的状态下能够降低导通电阻，根据本发明的半导体器件设置有栅电极，栅电极形成为栅极电极的范围从形成在N- 形成在P型半导体衬底中的选择性氧化膜的P型阱区，形成为使得源极区与栅电极相邻的P型源极区，形成在与栅极隔开的位置的P型漏极区 电极和形成为漂移区域围绕漏极区域的P型漂移区域（LP层），其特征在于，形成P型杂质层（FP层），使得杂质层与 漏极区域。