公开(公告)号：US20050106834A1

公开(公告)日：2005-05-19

申请号：US10700327

申请日：2003-11-03

申请人： Paul Andry ,  Jon Casey ,  Raymond Horton ,  Chiraq Patel ,  Edmund Sprogis ,  Brian Sundlof

发明人： Paul Andry ,  Jon Casey ,  Raymond Horton ,  Chiraq Patel ,  Edmund Sprogis ,  Brian Sundlof

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L21/76 ,  H01L23/14 ,  H01L25/04 ,  H01L25/18 ,  H05K3/34

CPC分类号： H01L21/486 ,  H01L23/147 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

摘要： A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.

摘要翻译： 一种用于在晶片中填充通孔，特别是初始盲孔的方法，以及用于执行该方法的各种装置，包括从通孔排出空气; 捕获晶片的至少一部分和用于在两个表面之间填充通孔的糊状物; 并对该糊状物加压以填充通孔。

公开(公告)号：US20050121768A1

公开(公告)日：2005-06-09

申请号：US10729254

申请日：2003-12-05

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20060027934A1

公开(公告)日：2006-02-09

申请号：US11242221

申请日：2005-10-03

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

IPC分类号： H01L23/48

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20080036084A1

公开(公告)日：2008-02-14

申请号：US11341458

申请日：2006-01-30

申请人： Leena Buchwalter ,  Paul Andry ,  Matthew Farinelli ,  Sherif Goma ,  Raymond Horton ,  Edmund Sprogis

发明人： Leena Buchwalter ,  Paul Andry ,  Matthew Farinelli ,  Sherif Goma ,  Raymond Horton ,  Edmund Sprogis

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

摘要： A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

摘要翻译： 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US20070048896A1

公开(公告)日：2007-03-01

申请号：US11214602

申请日：2005-08-30

申请人： Paul Andry ,  Chirag Patel ,  Edmund Sprogis ,  Cornelia Tsang

发明人： Paul Andry ,  Chirag Patel ,  Edmund Sprogis ,  Cornelia Tsang

IPC分类号： H01L21/00

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

摘要： Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

摘要翻译： 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：US20070222065A1

公开(公告)日：2007-09-27

申请号：US11385121

申请日：2006-03-21

申请人： Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

发明人： Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

IPC分类号： H01L21/00 ,  H01L23/34

CPC分类号： H01L24/81 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/81001 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/20109 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

摘要翻译： 一种电子潜水及其制造方法。 所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准 集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

公开(公告)号：US20110290402A1

公开(公告)日：2011-12-01

申请号：US12788832

申请日：2010-05-27

申请人： Paul Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

发明人： Paul Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC分类号： B32B33/00 ,  B29C65/16

CPC分类号： H01L21/67132 ,  C09J5/06 ,  C09J2203/326 ,  C09J2479/08 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68381 ,  Y10T156/1158

摘要： A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.

摘要翻译： 一种用于将处理器附接到晶片的方法，所述晶片包括集成电路（IC），包括在所述晶片上形成粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，所述聚酰亚胺基聚合物构造成经受超过约280℃的温度下的加工 C。; 以及使用所述粘合剂层将处理器粘附到所述晶片。 一种用于将处理器附接到晶片的系统，包括IC的晶片包括位于晶片上的粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，其被配置为经受超过约280℃的温度下的加工; 以及使用粘合剂层粘附到晶片的处理器。

公开(公告)号：US20070045844A1

公开(公告)日：2007-03-01

申请号：US11211116

申请日：2005-08-24

申请人： Paul Andry ,  Cyril Cabral ,  Kenneth Rodbell ,  Robert Wisnieff

发明人： Paul Andry ,  Cyril Cabral ,  Kenneth Rodbell ,  Robert Wisnieff

IPC分类号： H01L23/48

CPC分类号： H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

摘要： A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.

摘要翻译： 一种结构及其形成方法。 该结构包括一个包括N个芯片电极焊盘的集成电路，其中N是正整数，并且其中N个芯片电极焊盘电连接到集成电路上的多个器件。 该结构还包括对应于N个芯片电焊盘的N个焊料凸块。 半导体插入式屏蔽夹在集成电路和N个焊料凸块之间。 该结构还包括通过半导体插入屏蔽的N个导体（i）和（ii）将N个焊料凸块电连接到N个芯片电极焊盘。

公开(公告)号：US20050082676A1

公开(公告)日：2005-04-21

申请号：US10686640

申请日：2003-10-17

申请人： Paul Andry ,  Leena Buchwalter ,  Russell Budd ,  Thomas Wassick

发明人： Paul Andry ,  Leena Buchwalter ,  Russell Budd ,  Thomas Wassick

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.

摘要翻译： 该公开内容教导了使用金属的激光辅助化学气相沉积在硅或玻璃基板中填充深通孔或者封装深导电糊填充通孔的方法。 该方法使用连续波或脉冲激光器通过选择激光波长来选择性地加热通孔底部和生长金属填充物，使得硅和/或玻璃不以任何可察觉的方式吸收激光的能量以在场中沉积 。 或者，可以使用全息掩模或微透镜阵列来将激光束聚焦到通孔以用金属填充它们。 以大约的沉积速率，以z方向以受控方式远离激光器移动衬底，从而使激光加热聚焦在生长金属填充物的表面区域上。

公开(公告)号：US20060103011A1

公开(公告)日：2006-05-18

申请号：US10987985

申请日：2004-11-12

申请人： Paul Andry ,  Evan Colgan ,  Lawrence Mok ,  Chirag Patel ,  David Seeger

发明人： Paul Andry ,  Evan Colgan ,  Lawrence Mok ,  Chirag Patel ,  David Seeger

IPC分类号： H01L23/34

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2224/0401

摘要： Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.