公开(公告)号：US20240243021A1

公开(公告)日：2024-07-18

申请号：US18413041

申请日：2024-01-16

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L23/13 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/15153 ,  H01L2924/15311

摘要： A package carrier includes a signal board, a power board and a connection layer. The signal board includes a plurality of first circuits. The power board includes a plurality of second circuits. A line width of each of the first circuits is less than a line width of each of the second circuits, and a first thickness of the signal board is less than a second thickness of the power board. The connection layer is disposed between the signal board and the power board, wherein the power board is electrically connected to the signal board through the connection layer.

公开(公告)号：US09257379B2

公开(公告)日：2016-02-09

申请号：US13417858

申请日：2012-03-12

申请人： Tzyy-Jang Tseng ,  Chung-W. Ho

发明人： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC分类号： H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2221/6835 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

摘要： A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

摘要翻译： 提供了一种无芯封装基板，其包括：具有至少介电层，至少布线层和多​​个导电元件的电路积累结构，多个电焊垫嵌入至少一个介电层中的最下面的一个， 形成在所述至少一个布线层的最上面的多个金属凸块，以及形成在所述电路堆积结构和所述金属凸块的最上面的表面上的介电钝化层，所述金属凸块从所述电介质钝化 层。 金属凸块各自具有金属柱部分和与金属柱部分一体连接的翼部，使得金属凸块和半导体芯片之间的结合力由金属凸块的翼部的整个顶表面提高 完全暴露

公开(公告)号：US20120228015A1

公开(公告)日：2012-09-13

申请号：US13346738

申请日：2012-01-10

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H05K1/16 ,  H05K3/10 ,  H05K3/46 ,  H05K3/30 ,  H05K3/06 ,  H05K3/36 ,  H05K1/00 ,  H05K3/42

CPC分类号： H05K1/185 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2924/12042 ,  H05K1/116 ,  H05K3/0097 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09718 ,  H05K2203/1469 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A process of electronic structure is provided. First, a carrier board is provided, in which the carrier board has a first surface. Next, a first release layer is formed on the first surface of the carrier board. The first release layer has property of withstanding high-temperature and temporary adhesion capability and the first release layer entirely or mostly overlays the first surface. Then, a built-up structure is formed on the first release layer. Finally, a separating process is performed so that the built-up structure is separated from the carrier board to form an electronic structure.

摘要翻译： 提供电子结构的过程。 首先，提供载体板，其中承载板具有第一表面。 接下来，在载板的第一表面上形成第一释放层。 第一释放层具有耐高温和临时粘合能力的特性，并且第一释放层完全或大体上覆盖在第一表面上。 然后，在第一剥离层上形成积层结构。 最后，进行分离处理，使得积层结构与载体板分离以形成电子结构。

公开(公告)号：US07540969B2

公开(公告)日：2009-06-02

申请号：US11565836

申请日：2006-12-01

申请人： Chung W. Ho ,  Leo Shen

发明人： Chung W. Ho ,  Leo Shen

IPC分类号： H01B13/00

CPC分类号： H01L23/142 ,  H01L23/49861 ,  H01L33/64 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K1/056 ,  H05K3/44 ,  H05K2201/0355 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0323 ,  H05K2203/0369 ,  H01L2924/00

摘要： A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself.

摘要翻译： 提供了一种高导热电路基板的制造工艺。 首先，提供金属芯基板，然后以不同的蚀刻速度蚀刻金属芯基板。 之后，在蚀刻后的金属芯基板的两面分别形成两层绝缘层。 此外，作为选择，分别在金属芯基板的两侧形成两个导电层，并且在绝缘层的顶部。 根据适合于产品的设计对导电层进行图案化。 由于作为上述制造工艺制造的高导热电路基板主要包括金属芯基板，所以有助于提高电路基板本身的热传导。

公开(公告)号：US06562656B1

公开(公告)日：2003-05-13

申请号：US09888258

申请日：2001-06-25

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L2144

CPC分类号： H01L21/4857 ,  H01L21/4853 ,  H01L21/52 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H05K3/20 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2924/00

摘要： The process of the invention starts with a metal panel, overlying the metal panel is created an interconnect substrate making use of BUM and thin film processing technology while the process of the invention enables the use of stacked vias and merged vias for the connection of the flip chip bumps. The process of the invention creates, for instance, two patterned layers on the surface of the metal panel whereby the metal panel is used as the ground terminal of the power supply. The first layer that is created on the surface of the metal panel can be the power supply layer (this layer can also be used for some fan-out interconnect lines), the second layer that is created on the surface of the metal panel is primarily used for (fan-out) interconnect lines. The flip chip bumps are, under the process of the invention, connected to the second layer of the interconnect substrate. Where the BGA balls also reside on the same surface as the flip chip bumps, the process of the invention does not require any additional structures such as a dam for the containment of insulating encapsulation material (underfill) that at times is provided around a perimeter of a well into which a flip chip is inserted, making the process of the invention most cost effective.

摘要翻译： 本发明的方法从金属面板开始，在金属面板的上方形成利用BUM和薄膜处理技术的互连衬底，而本发明的方法能够使用堆叠的通孔和合并的通孔来连接翻转 芯片颠簸 本发明的方法在金属板的表面上形成例如两个图案化层，由此金属板用作电源的接地端子。 在金属面板的表面上形成的第一层可以是电源层（该层也可以用于一些扇出的互连线），在金属面板的表面上形成的第二层主要是 用于（扇出）互连线。 在本发明的过程中，倒装芯片凸块连接到互连衬底的第二层。 当BGA球也位于与倒装芯片凸块相同的表面上时，本发明的方法不需要任何附加结构，例如用于容纳绝缘包封材料（底部填充物）的坝，其有时被设置在 其中插入倒装芯片的阱，使得本发明的方法最具成本效益。

公开(公告)号：US4812191A

公开(公告)日：1989-03-14

申请号：US55794

申请日：1987-06-01

申请人： Chung W. Ho ,  B. Y. Min

发明人： Chung W. Ho ,  B. Y. Min

IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/20 ,  H05K3/46 ,  B32B31/00 ,  B44C3/02

CPC分类号： H05K3/4682 ,  H01L21/4857 ,  H01L23/5383 ,  H05K3/467 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/0058 ,  H05K3/20 ,  Y10S156/922 ,  Y10T156/11

摘要： A method of fabricating a high density electrical interconnection member by forming a composite interconnection from metallic conductors on cured liquid polymer resin on substrate. The resin is cured at an elevated temperature to form a solid dielectric layer. Successive metallic and dielectric layers form an interconnection subassembly with the coefficient of thermal expansion of the substrate being less than the subassembly. The temperature of the subassembly is lowered placing it in tension. A support member is adhered to the exposed surface of the subassembly and the substrate removed. Multiple subassemblies can be joined together physically and electricaly to form a complex device for interconnecting a plurality of integrated circuit chips for high performance computer applications.

摘要翻译： 通过在基板上固化的液体聚合物树脂上的金属导体形成复合互连来制造高密度电互连部件的方法。 树脂在升高的温度下固化以形成固体介电层。 连续的金属和电介质层形成互连子组件，其中衬底的热膨胀系数小于子组件。 子组件的温度降低，使其处于张紧状态。 支撑构件粘附到子组件的暴露表面并移除衬底。 多个子组件可以物理和电气连接在一起以形成用于互连用于高性能计算机应用的多个集成电路芯片的复杂器件。

公开(公告)号：US11217551B1

公开(公告)日：2022-01-04

申请号：US17209230

申请日：2021-03-23

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683

摘要： A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.

公开(公告)号：US09137899B2

公开(公告)日：2015-09-15

申请号：US13346738

申请日：2012-01-10

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H05K3/00 ,  H05K1/18 ,  H01L21/683 ,  H05K1/11 ,  H05K3/46 ,  H01L21/48 ,  H01L23/00

CPC分类号： H05K1/185 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2924/12042 ,  H05K1/116 ,  H05K3/0097 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09718 ,  H05K2203/1469 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A process of electronic structure is provided. First, a carrier board is provided, in which the carrier board has a first surface. Next, a first release layer is formed on the first surface of the carrier board. The first release layer has property of withstanding high-temperature and temporary adhesion capability and the first release layer entirely or mostly overlays the first surface. Then, a built-up structure is formed on the first release layer. Finally, a separating process is performed so that the built-up structure is separated from the carrier board to form an electronic structure.

摘要翻译： 提供电子结构的过程。 首先，提供载体板，其中承载板具有第一表面。 接下来，在载板的第一表面上形成第一释放层。 第一释放层具有耐高温和临时粘合能力的特性，并且第一释放层完全或大体上覆盖在第一表面上。 然后，在第一剥离层上形成积层结构。 最后，进行分离处理，使得积层结构与载体板分离以形成电子结构。

公开(公告)号：US08939188B2

公开(公告)日：2015-01-27

申请号：US13471429

申请日：2012-05-14

申请人： Chung W. Ho ,  Chih-Hsien Cheng

发明人： Chung W. Ho ,  Chih-Hsien Cheng

IPC分类号： B32B38/10

CPC分类号： B26F3/004 ,  B26F3/008 ,  Y10T156/1137 ,  Y10T156/1939

摘要： An edge separation equipment and an operating method thereof are suitable for a carrier and a circuit board in a coreless process. The carrier is attached to the circuit board by a mechanically separable interface, and the edge separation equipment is used to separate the edge of the carrier from the edge of the circuit board. The edge separation equipment includes a platform, a supporting device and a wind knife device. The platform has a supporting surface on which the carrier or the circuit board is mounted. The supporting device is configured at a side of the platform. The wind knife device is configured on the supporting device, and the air jet supplied by the wind knife device blows toward the edge of the carrier and the edge of the circuit board, such that there is an edge separation width between the carrier and the circuit board.

摘要翻译： 边缘分离设备及其操作方法适用于无芯过程中的载体和电路板。 载体通过机械可分离的接口连接到电路板，并且边缘分离设备用于将载体的边缘与电路板的边缘分离。 边缘分离设备包括平台，支撑装置和风刀装置。 平台具有载体或电路板安装在其上的支撑表面。 支撑装置配置在平台的一侧。 风刀装置构造在支撑装置上，并且由风刀装置供应的空气喷射朝着载体的边缘和电路板的边缘吹动，使得在载体和电路之间存在边缘分离宽度 板。

公开(公告)号：US08624382B2

公开(公告)日：2014-01-07

申请号：US13542928

申请日：2012-07-06

申请人： Tzyy-Jang Tseng ,  Chung-W. Ho

发明人： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC分类号： H01L23/14 ,  H01L23/48

CPC分类号： H01L24/19 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029

摘要： A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.

摘要翻译： 封装基板包括第一介电层; 多个第一导电焊盘，其嵌入并暴露于所述第一介电层的第一表面; 第一电路层，其被嵌入并暴露于所述第一介电层的第二表面; 设置在第一电介质层中的多个第一金属凸块，每个第一金属凸块具有嵌入在第一电路层中的第一端和与第一端相对的第二端并且设置在第一导电焊盘之一上，导电种子层 设置在第一电路层和第一电介质层之间以及第一电路层和第一金属凸块之间; 布置在第一电路层和第一介电层上的叠层结构; 以及设置在所述积层结构上的多个第二导电焊盘。 包装衬底具有改善的超翘曲问题。