公开(公告)号：US08446017B2

公开(公告)日：2013-05-21

申请号：US12562387

申请日：2009-09-18

申请人： Jong Sik Paek ,  In Bae Park ,  Chang Deok Lee

发明人： Jong Sik Paek ,  In Bae Park ,  Chang Deok Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/221 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/83

摘要： A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.

摘要翻译： 公开了一种可堆叠的晶片级封装及其制造方法。 在可堆叠晶片级封装中，接合焊盘（或再分配层）被布置在底部半导体管芯上，并且金属柱形成在位于底部半导体管芯的边缘周围的一些接合焊盘上。 顶部半导体管芯电连接到其上未形成金属柱的其它接合焊盘，通过导电凸块定位在底部半导体管芯的中心附近。 金属柱和顶部半导体管芯由密封剂封装。 电连接到金属柱的多个互连图案形成在密封剂的表面上。 焊球附接到互连图案。 由于这种堆叠结构，晶片级封装的厚度和占地面积减小。 因此，晶片级封装非常适合于移动应用。

公开(公告)号：US09048241B2

公开(公告)日：2015-06-02

申请号：US14063394

申请日：2013-10-25

申请人： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

发明人： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

IPC分类号： H01L23/02 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L24/03 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/83

摘要： A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

摘要翻译： 公开了一种利用再分配层耦合堆叠管芯的半导体器件，其可以包括第一半导体管芯，其具有包括接合焊盘的第一表面，与第一表面相对的第二表面以及第一和第二表面之间的倾斜侧表面， 第一个模具的截面形状为梯形。 具有第一表面的第二半导体管芯可以结合到第一管芯的第二表面，其中第二管芯的第一表面可以包括接合焊盘。 钝化层可以形成在第一模具的第一表面和倾斜的侧表面上以及第二模具的第一表面上。 可以在钝化层上形成再分配层，电耦合第一和第二裸片上的接合焊盘。 导电柱可以从第二管芯上的焊盘延伸到第二再分布层。

公开(公告)号：US06987319B1

公开(公告)日：2006-01-17

申请号：US11006210

申请日：2004-12-06

申请人： Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

发明人： Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/03 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19041

摘要： A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

摘要翻译： 晶片级芯片级封装包括具有平面顶表面和底表面的半导体管芯和在区域阵列中形成在顶表面处的多个金属焊盘。 第一保护层形成在半导体管芯的顶表面上，第一保护层具有多个用于允许金属焊盘向上打开的第一孔。 在所述第一保护层的表面上形成第二保护层，所述第二保护层具有多个第二孔，所述多个第二孔大于所述第一保护层的第一孔，并且过度相应地使所述金属垫和所述第一保护层 层暴露于半导体管芯的外部。 焊球与每个金属焊盘熔合，每个金属焊盘通过第一保护层的第一孔和第二保护层的第二孔向外开口。

公开(公告)号：US09748154B1

公开(公告)日：2017-08-29

申请号：US12939588

申请日：2010-11-04

申请人： Boo Yang Jung ,  Jong Sik Paek ,  Choon Heung Lee ,  In Bae Park ,  Sang Won Kim ,  Sung Kyu Kim ,  Sang Gyu Lee

发明人： Boo Yang Jung ,  Jong Sik Paek ,  Choon Heung Lee ,  In Bae Park ,  Sang Won Kim ,  Sung Kyu Kim ,  Sang Gyu Lee

IPC分类号： H01L23/00

CPC分类号： H01L24/09 ,  H01L21/56 ,  H01L23/00 ,  H01L23/3135 ,  H01L23/522 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/15172 ,  H01L2924/18162 ,  H01L2924/3511

摘要： A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

公开(公告)号：US06841874B1

公开(公告)日：2005-01-11

申请号：US10285978

申请日：2002-11-01

申请人： Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

发明人： Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

IPC分类号： H01L23/31 ,  H01L23/485

CPC分类号： H01L24/03 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19041

摘要： A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

摘要翻译： 晶片级芯片级封装包括具有平面顶表面和底表面的半导体管芯和在区域阵列中形成在顶表面处的多个金属焊盘。 第一保护层形成在半导体管芯的顶表面上，第一保护层具有多个用于允许金属焊盘向上打开的第一孔。 在所述第一保护层的表面上形成第二保护层，所述第二保护层具有多个第二孔，所述多个第二孔大于所述第一保护层的第一孔，并且过度相应地使所述金属垫和所述第一保护层 层暴露于半导体管芯的外部。 焊球与每个金属焊盘熔合，每个金属焊盘通过第一保护层的第一孔和第二保护层的第二孔向外开口。

公开(公告)号：US20150014830A1

公开(公告)日：2015-01-15

申请号：US14063394

申请日：2013-10-25

申请人： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

发明人： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

IPC分类号： H01L23/538 ,  H01L25/00

CPC分类号： H01L24/03 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/83

摘要： A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

摘要翻译： 公开了一种利用再分配层耦合堆叠管芯的半导体器件，其可以包括第一半导体管芯，其具有包括接合焊盘的第一表面，与第一表面相对的第二表面以及第一和第二表面之间的倾斜侧表面， 第一个模具的截面形状为梯形。 具有第一表面的第二半导体管芯可以结合到第一管芯的第二表面，其中第二管芯的第一表面可以包括接合焊盘。 钝化层可以形成在第一模具的第一表面和倾斜的侧表面上以及第二模具的第一表面上。 可以在钝化层上形成再分配层，电耦合第一和第二裸片上的接合焊盘。 导电柱可以从第二管芯上的焊盘延伸到第二再分布层。

公开(公告)号：US08362612B1

公开(公告)日：2013-01-29

申请号：US12728119

申请日：2010-03-19

申请人： Jong Sik Paek ,  Eun Sook Sohn ,  In Bae Park ,  Won Chul Do ,  Glenn A. Rinne

发明人： Jong Sik Paek ,  Eun Sook Sohn ,  In Bae Park ,  Won Chul Do ,  Glenn A. Rinne

IPC分类号： H01L21/00

CPC分类号： H01L21/76885 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00

摘要： A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

摘要翻译： 公开了一种半导体器件及其制造方法。 在半导体管芯上形成第一绝缘层，在第一绝缘层上形成与接合焊盘电连接的再分配层，第二绝缘层覆盖再分布层。 第二绝缘层由便宜的非感光材料制成。 因此，可以降低半导体器件的制造成本。

公开(公告)号：US09000586B2

公开(公告)日：2015-04-07

申请号：US13726917

申请日：2012-12-26

申请人： Won Chul Do ,  Doo Hyun Park ,  Jong Sik Paek ,  Ji Hun Lee ,  Seong Min Seo

发明人： Won Chul Do ,  Doo Hyun Park ,  Jong Sik Paek ,  Ji Hun Lee ,  Seong Min Seo

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L23/367 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683

CPC分类号： H01L21/4846 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.

摘要翻译： 提供一种半导体器件及其制造方法，该半导体器件具有不具有通过硅通孔的相对较薄厚度的中介层。 制造半导体器件的方法包括在虚设衬底上形成包括再分配层和电介质层的插入件，将半导体管芯连接到面向插入件上部的再分配层，通过使用封装，去除 所述虚拟衬底从所述插入器连接，并且将凸块连接到面向所述插入件的下部的再分配层。

公开(公告)号：US20150021767A1

公开(公告)日：2015-01-22

申请号：US14063829

申请日：2013-10-25

申请人： Doo Hyun Park ,  Seong Min Seo ,  Wang Gu Lee ,  Jong Sik Paek ,  Won Chul Do

发明人： Doo Hyun Park ,  Seong Min Seo ,  Wang Gu Lee ,  Jong Sik Paek ,  Won Chul Do

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/8192 ,  H01L2224/81986 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00

摘要： A semiconductor device with plated conductive pillar coupling is disclosed and may include a semiconductor die comprising a conductive pillar formed on a bond pad on the die, a substrate comprising an insulating layer with conductive patterns formed on a first surface of the substrate and a second surface opposite to the first surface, and a plating layer electrically coupling the conductive pillar and the bond pad on the first surface of the die to the conductive pattern on the first surface of the substrate. The conductive pillar, the conductive patterns, and the plating layer may comprise copper. The plating layer may fill a void between the copper pillar and the conductive pattern on the first surface of the substrate. The substrate may comprise a rigid circuit board, a flexible circuit board, a ceramic substrate, a semiconductor die, or semiconductor wafer.

摘要翻译： 公开了一种具有电镀导电柱形耦合的半导体器件，并且可以包括半导体管芯，该半导体管芯包括形成在管芯上的接合焊盘上的导电柱，衬底，其包括形成在衬底的第一表面上的导电图案的绝缘层， 以及电镀层，其将导电柱和焊盘的第一表面上的接合焊盘电耦合到基板的第一表面上的导电图案。 导电柱，导电图案和镀层可以包括铜。 镀层可以填充在基板的第一表面上的铜柱和导电图案之间的空隙。 衬底可以包括刚性电路板，柔性电路板，陶瓷衬底，半导体管芯或半导体晶片。

公开(公告)号：US06927478B2

公开(公告)日：2005-08-09

申请号：US10043946

申请日：2002-01-11

申请人： Jong Sik Paek

发明人： Jong Sik Paek

IPC分类号： H01L23/12 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package comprising a plurality of leads. Each of the leads defines opposed first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface. The first surface is oriented between the second and third surfaces. The semiconductor package further comprises first and second semiconductor dies which each define opposed first and second surfaces. Disposed on the first surface of the first semiconductor die are a plurality of bond pads, with bond pads also being disposed on the second surface of the semiconductor die. The first surface of the first semiconductor die is attached to the second surface of each of the leads, with the first surface of the second semiconductor die being attached to the second surface of the first semiconductor die. A plurality of conductive connectors or wires electrically connect the bond pads of the first and second semiconductor dies to respective ones of the leads. An encapsulating portion is applied to and at least partially encapsulates the leads, the first and second semiconductor dies, and the conductive connectors.