公开(公告)号：US6114098A

公开(公告)日：2000-09-05

申请号：US154935

申请日：1998-09-17

申请人： Bernd Karl Appelt ,  John Steven Kresge ,  John Matthew Lauffer ,  Kostas I. Papathomas

发明人： Bernd Karl Appelt ,  John Steven Kresge ,  John Matthew Lauffer ,  Kostas I. Papathomas

IPC分类号： H05K3/00 ,  H05K3/40 ,  G03F7/00

CPC分类号： H05K3/4053 ,  H05K2203/0191 ,  H05K3/0082 ,  H05K3/0094 ,  Y10T428/2809

摘要： An aperture in an electronic substrate is filled with a filling material without need for a specially built fill mask. A layer of tape or tentable photosensitive dielectric film is applied to one surface of the substrate covering the aperture. An opening is made in the tape or film by directing radiation through the aperture. Fill material is then forced through the opening to substantially fill the aperture. Protruding nubs may be removed to planarize the substrate surfaces.

摘要翻译： 电子基板中的孔填充有填充材料，而不需要特别构造的填充掩模。 将一层带或暂时的光敏电介质膜施加到覆盖孔的基板的一个表面上。 通过将辐射引导通过孔，在胶带或胶片中形成开口。 填充材料然后被迫穿过开口基本上填充孔。 可以去除凸起的凸块以使基底表面平坦化。

公开(公告)号：US5798563A

公开(公告)日：1998-08-25

申请号：US790245

申请日：1997-01-28

申请人： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

发明人： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46 ,  H01L23/495 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49894 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49838 ,  H01L24/73 ,  H01L24/81 ,  H05K3/4602 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/056 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2203/1581 ,  H05K3/4069 ,  H05K3/4641 ,  Y10T29/49165

摘要： The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 3.5% The invention also relates to methods of making the dielectric coated chip carrier.

摘要翻译： 本发明提供了一种特别适用于倒装芯片的有机芯片载体，包括有机电介质层，设置在电介质层上的第一电路层，设置在第一绝缘层和第一层电路上的有机构象涂层，以及 具有线宽度为约2.0密耳或更小，优选约1.0密耳或更小，优选约0.7密耳的线宽和约1.5密耳或更小，优选约1.1密耳或更小的线之间的间隔的细线电路层， 构象层。 优选地，电介质层不含编织玻璃纤维。 构象涂层优选具有约1.5至约3.5的介电常数和大于约3.5％的平均化百分比本发明还涉及制备电介质涂覆的芯片载体的方法。

公开(公告)号：US5829124A

公开(公告)日：1998-11-03

申请号：US580678

申请日：1995-12-29

申请人： John Steven Kresge ,  David Noel Light

发明人： John Steven Kresge ,  David Noel Light

IPC分类号： H05K3/34 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

CPC分类号： H05K3/4015 ,  H05K1/113 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/1025 ,  H05K2203/0278 ,  H05K2203/1394 ,  H05K3/0094 ,  H05K3/4007 ,  H05K3/4614 ,  Y10T29/4913 ,  Y10T29/49144

摘要： A method for attaching pads to a high density printed circuit board (PCB) having a plurality of through-holes opening on the top surface. The method includes forming a plurality of pads on a carrier sheet so that each of said pads have a copper layer proximate to said carrier sheet and a joining metal layer formed on top of said copper layer, positioning the plurality of pads on the carrier sheet so that they are aligned with the through-hole pattern on the top surface of the PCB, laminating the pads to the through-holes on the top surface using the joining metal, and separating the carrier sheet from the plurality of pads that are joined to the through-holes so that the copper layer is exposed. The pads may comprise a variety of shapes such as disk-shaped, elongated, or rectangular, and can cover one or multiple through-holes. An electrical component may be soldered to the pad. The method advantageously prevents wicking of the solderball volume into the through-hole, thereby increasing yield and part reliability. In one embodiment, the pad and through-hole may be compressed so that the top surface of the pad is even (flush) with the top surface of the external dielectric surface.

摘要翻译： 一种用于将焊盘附接到具有在顶表面上开口的多个通孔的高密度印刷电路板（PCB）的方法。 该方法包括在载体片上形成多个焊盘，使得每个焊盘具有靠近所述载体片的铜层和形成在所述铜层顶部的接合金属层，将多个焊盘定位在载体片上 它们与PCB的顶表面上的通孔图案对准，使用接合金属将焊盘层压到顶表面上的通孔，并将载体片从与多个焊盘接合的多个焊盘分离 通孔使铜层露出。 垫可以包括各种形状，例如盘形，细长或矩形，并且可以覆盖一个或多个通孔。 电气部件可以焊接到焊盘。 该方法有利地防止了焊球体积进入通孔，从而提高了产量和部件的可靠性。 在一个实施例中，垫和通孔可以被压缩，使得垫的顶表面与外部电介质表面的顶表面均匀（齐平）。

公开(公告)号：US5781413A

公开(公告)日：1998-07-14

申请号：US719826

申请日：1996-09-30

申请人： Wayne John Howell ,  John Steven Kresge ,  David Brian Stone ,  James Robert Wilcox

发明人： Wayne John Howell ,  John Steven Kresge ,  David Brian Stone ,  James Robert Wilcox

IPC分类号： H01L21/98 ,  H01L25/065 ,  H05K1/11 ,  H05K1/14 ,  H05K7/02

CPC分类号： H05K1/141 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06596 ,  H05K1/114 ,  H05K2201/10378 ,  H05K2201/10734

摘要： A technique is disclosed for forming a chip cube from a plurality of chips laminated together in front-to-back relationship, the edges of the chip forming a cube face having a set of connectors for each chip thereon. A number "X" of functional chips is required for the operation, and "X+Y" is the number of chips provided in the stack such that there is Y number of chips greater than the number of functional chips required. If any number of chips equal to Y or less are found to be defective, there are enough chips remaining to perform the required function. Thereafter X number of good chips are connected to output circuitry through an interposer. Electrical connectors are provided on all of the IC chips. Contact pads for all of the connectors are provided on one face, and outlet pads are provided on the opposite face of the interposer for at least Y number of outlets. The interposer has vias at least equal to the number of outlet pads. After assembly, the chips are burnt-in, and if there are enough functional chips after burn-in, the interposer is wired to connect X number of sets of chip pads and the outlet pads through the vias. The chip stack is mounted on the interposer wherein all of the connectors on the cube face are connected to all of the chip mounting pads, but only those which have been selected for functioning chips are connected through the vias to the outlet pads.

摘要翻译： 公开了一种用于从前后关系层叠在一起的多个芯片形成芯片立方体的技术，芯片的边缘形成具有用于其每个芯片的一组连接器的立方体面。 操作需要一个“X”功能芯片，“X + Y”是堆叠中提供的芯片数量，使得Y芯片数量大于所需的功能芯片数量。 如果发现任何数量的等于或等于Y的芯片是有缺陷的，则剩余足够的芯片来执行所需的功能。 此后，X个好的芯片通过插入器连接到输出电路。 所有IC芯片都提供电连接器。 用于所有连接器的接触垫设置在一个面上，并且出口垫设置在插入件的相对面上，用于至少Y个出口。 插入器具有至少等于插座数量的通孔。 组装之后，芯片烧坏，如果老化后有足够的功能芯片，则插入器通过通孔连接X个芯片组和出口焊盘。 芯片堆叠安装在插入器上，其中立方体表面上的所有连接器都连接到所有的芯片安装焊盘，但只有那些已被选择用于功能芯片的连接器通过通孔连接到出口焊盘。

公开(公告)号：US08198551B2

公开(公告)日：2012-06-12

申请号：US12782187

申请日：2010-05-18

申请人： Robert M. Japp ,  Kostas Papathomas ,  John Steven Kresge ,  Timothy Antesberger

发明人： Robert M. Japp ,  Kostas Papathomas ,  John Steven Kresge ,  Timothy Antesberger

IPC分类号： H05K1/11

CPC分类号： H05K3/4641 ,  H05K3/4617 ,  H05K2201/068 ,  Y10T29/49117

摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

摘要翻译： 适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。 芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。 导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。 还提供了制造电源芯和电路化基板的方法。 使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题 。

公开(公告)号：US6006428A

公开(公告)日：1999-12-28

申请号：US53874

申请日：1998-04-01

申请人： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

发明人： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC分类号： H01L23/49894 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49838 ,  H01L24/73 ,  H01L24/81 ,  H05K3/4602 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/056 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2203/1581 ,  H05K3/4069 ,  H05K3/4641 ,  Y10T29/49165

摘要： The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

摘要翻译： 本发明提供了一种特别适用于倒装芯片的有机芯片载体，包括有机电介质层，设置在电介质层上的第一电路层，设置在第一绝缘层和第一层电路上的有机构象涂层，以及 具有线宽度为约2.0密耳或更小，优选约1.0密耳或更小，优选约0.7密耳的线宽和约1.5密耳或更小，优选约1.1密耳或更小的线之间的间隔的细线电路层， 构象层。 优选地，电介质层不含编织玻璃纤维。 构象涂层优选具有约1.5至约3.5的介电常数和大于约30％的百分比平面化。 本发明还涉及制造电介质涂覆的芯片载体的方法。

公开(公告)号：US06259037B1

公开(公告)日：2001-07-10

申请号：US09411871

申请日：1999-10-04

申请人： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

发明人： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

IPC分类号： H05K116

CPC分类号： H01L23/49894 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49838 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/056 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2203/1581 ,  Y10T29/49165 ,  H01L2924/00

摘要： The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

摘要翻译： 本发明提供了特别适用于倒装芯片的有机芯片载体。 芯片载体包括有机电介质层，设置在电介质层上的第一电路层，设置在电介质第一层和第一层电路上的有机构象涂层，以及细线电路层。 细线电路的线宽为约2.0密耳或更小，优选约1.0密耳或更小，更优选约0.7密耳，线之间的间隔为约1.5密耳或更小，优选约1.1密耳或更小。 优选地，电介质层不含编织玻璃纤维。 构象涂层优选具有约1.5至约3.5的介电常数和大于约30％的百分比平面化。 本发明还涉及制造电介质涂覆的芯片载体的方法。

公开(公告)号：US6066808A

公开(公告)日：2000-05-23

申请号：US058908

申请日：1998-04-10

申请人： John Steven Kresge ,  David Noel Light

发明人： John Steven Kresge ,  David Noel Light

IPC分类号： H05K3/34 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H01R9/09

CPC分类号： H05K3/4015 ,  H05K1/113 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/1025 ,  H05K2203/0278 ,  H05K2203/1394 ,  H05K3/0094 ,  H05K3/4007 ,  H05K3/4614 ,  Y10T29/4913 ,  Y10T29/49144

摘要： Pads which are attached to a high density printed circuit board (PCB) having a plurality of through-holes opening on the top surface. A plurality of pads are formed on a carrier sheet so that each of the pads have a copper layer proximate to the carrier sheet and a joining metal layer formed on top of said copper layer. The plurality of pads are positioned on the carrier sheet so that they are aligned with the through-hole pattern on the top surface of the PCB, the pads bing laminated to the through-holes on the top surface using the joining metal, and the carrier sheet being separated from the plurality of pads that are joined to the through-holes so that the copper layer is exposed. The pads may possess a variety of shapes such as disk-shaped, elongated, or rectangular, and can cover one or multiple through-holes. An electrical component may be soldered to the pad. The pad and through-hole may be compressed so that the top surface of the pad is even (flush) with the top surface of an external dielectric surface.

摘要翻译： 连接到具有在顶表面上开口的多个通孔的高密度印刷电路板（PCB）的垫。 多个焊盘形成在载体片上，使得每个焊盘具有靠近载体片的铜层和形成在所述铜层顶部上的接合金属层。 多个焊盘定位在载体片上，使得它们与PCB的顶表面上的通孔图案对准，使用接合金属将衬垫层压到顶表面上的通孔，并且载体 片与从连接到通孔的多个焊盘分开，以使铜层露出。 垫可以具有各种形状，例如盘形，细长或矩形，并且可以覆盖一个或多个通孔。 电气部件可以焊接到焊盘。 垫和通孔可以被压缩，使得垫的顶表面与外部电介质表面的顶表面均匀（齐平）。

公开(公告)号：US5736679A

公开(公告)日：1998-04-07

申请号：US579618

申请日：1995-12-26

申请人： John Steven Kresge ,  David Noel Light ,  James Robert Wilcox

发明人： John Steven Kresge ,  David Noel Light ,  James Robert Wilcox

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00

CPC分类号： H05K1/0271 ,  H05K1/116 ,  H05K3/4623 ,  H05K2201/0382 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K3/429 ,  Y10T29/49126

摘要： A novel through-hole interconnect for connecting a power plane conductor to a through-hole includes a central pad connected to the through-hole and a deformable hinge that connects the central pad with the power plane conductor in a multilayer circuit board. The central pad and hinge are defined by a non-continuous area removed from the plane conductor. Preferably this area has a C-shape. During the compression process to join the core assemblies, deformation of the hinge advantageously absorbs the shear forces and allows the power plane beyond the hinge to remain substantially planar. The resulting multilayer laminated circuit board includes a plurality of cores laminated together in a stacked configuration and a plurality of plated through-holes defined in said multilayer laminated circuit board each of which is connected to a plane conductor by a hinge deformed so that the interconnect area is aligned outside of a plane defined by the plane conductor. The hinged interconnect avoids shearing problems and thereby improves the reliability of the connection between the through-hole and the power plane, increasing the manufacturing yield and reducing costs. Furthermore, the hinged interconnect minimizes or eliminates internal plane distortion over the signal lines because the reference plane deformation is localized and the signal lines lie substantially outside the area of localized deformation and therefore the impedance seen by the signal lines is substantially unaffected by the compression-induced deformation.

摘要翻译： 用于将电源平面导体连接到通孔的新型通孔互连件包括连接到通孔的中心焊盘和将多个电路板中的中心焊盘与电源平面导体连接的可变形铰链。 中心垫和铰链由从平面导体去除的非连续区域限定。 优选地，该区域具有C形。 在连接芯组件的压缩过程期间，铰链的变形有利地吸收剪切力并允许超过铰链的动力平面保持基本上平面。 所得到的多层叠层电路板包括层叠在一起的多个芯体和限定在所述多层叠层电路板中的多个电镀通孔，所述多个层叠电路板通过铰链变形而连接到平面导体，使得互连面积 在由平面导体限定的平面外对齐。 铰链互连避免了剪切问题，从而提高了通孔和动力平面之间的连接的可靠性，提高了制造成品率并降低了成本。 此外，由于参考平面变形是局部化的并且信号线基本上位于局部变形区域之外，所以铰链式互连最小化或消除了信号线上的内部平面失真，因此信号线看到的阻抗基本上不受压缩 - 诱发变形。