公开(公告)号：US06900545B1

公开(公告)日：2005-05-31

申请号：US09526957

申请日：2000-03-16

Applicant: Robert David Sebesta ,  James Warren Wilson

Inventor： Robert David Sebesta ,  James Warren Wilson

IPC: H01L23/498 ,  H05K1/02 ,  H05K3/24 ,  H05K3/42 ,  H01L23/02 ,  H01L29/40

CPC classification number: H05K1/0265 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.

Abstract translation: 一种电子结构和相关的制造方法，其包括具有附接的电路元件的衬底和不同厚度的导电接合焊盘。 与垫厚相关的垫类别包括厚垫（17至50微米），中垫（10-17微米）和薄垫（3至10微米）。 使用厚焊盘将球栅阵列（BGA）耦合到具有BGA与电路卡的附接的基板。 介质垫可用于通过使用接口小的焊球将芯片倒装芯片连接到基板。 涂覆有镍 - 金层的薄铜焊盘可用于通过引线接口将芯片耦合到衬底。 电结构包括具有不同厚度的两个焊盘的电耦合，使得焊盘位于衬底的相同表面上或者位于衬底的相对侧上。

公开(公告)号：US06296897B1

公开(公告)日：2001-10-02

申请号：US09133029

申请日：1998-08-12

Applicant: John Joseph Konrad ,  Konstantinos I. Papathomas ,  Timothy Leroy Wells ,  James Warren Wilson

Inventor： John Joseph Konrad ,  Konstantinos I. Papathomas ,  Timothy Leroy Wells ,  James Warren Wilson

IPC: B05D512

CPC classification number: C23C18/1651 ,  C23C18/1844 ,  H05K3/184 ,  H05K3/244 ,  H05K3/26 ,  H05K2201/0761 ,  H05K2203/0796 ,  Y10T428/24917

Abstract: Printed circuit boards, cards and chip carriers are fabricated by treating an already circuitized substrate with a swelling agent, then treating the circuitized substrate with a composition containing an alkaline permanganate, a chromate and/or chlorite and then applying a metal layer to coat the circuitized portion of the substrate.

Abstract translation: 印刷电路板，卡片和芯片载体通过用溶胀剂处理已经电路化的基底，然后用含有碱性高锰酸盐，铬酸盐和/或亚氯酸盐的组合物处理电路化基底，然后施加金属层以涂覆电路化 部分基板。

公开(公告)号：US06259037B1

公开(公告)日：2001-07-10

申请号：US09411871

申请日：1999-10-04

Applicant: Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

Inventor： Natalie Barbara Feilchenfeld ,  John Steven Kresge ,  Scott Preston Moore ,  Ronald Peter Nowak ,  James Warren Wilson

IPC: H05K116

CPC classification number: H01L23/49894 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49838 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/056 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2203/1581 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

Abstract translation: 本发明提供了特别适用于倒装芯片的有机芯片载体。 芯片载体包括有机电介质层，设置在电介质层上的第一电路层，设置在电介质第一层和第一层电路上的有机构象涂层，以及细线电路层。 细线电路的线宽为约2.0密耳或更小，优选约1.0密耳或更小，更优选约0.7密耳，线之间的间隔为约1.5密耳或更小，优选约1.1密耳或更小。 优选地，电介质层不含编织玻璃纤维。 构象涂层优选具有约1.5至约3.5的介电常数和大于约30％的百分比平面化。 本发明还涉及制造电介质涂覆的芯片载体的方法。

公开(公告)号：US6013417A

公开(公告)日：2000-01-11

申请号：US54374

申请日：1998-04-02

Applicant: Robert David Sebesta ,  James Warren Wilson

Inventor： Robert David Sebesta ,  James Warren Wilson

IPC: G03F7/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K3/064 ,  G03F7/0035 ,  H05K3/0094 ,  H05K2203/0588 ,  H05K2203/068 ,  H05K2203/1394 ,  H05K2203/1572 ,  H05K3/427

Abstract: Circuitry is formed on a substrate having at least one plated through-hole employing two different photoresist materials. A first photoresist is applied on a conductive layer located on a substrate and is developed to define a desired conductive circuit pattern. A second photoresist is laminated onto the structure and is developed so that the second photoresist material remains in the vicinity of the through-hole. The conductive layer is etched to provide the desired circuit pattern, and the remaining portions of the second and first photoresists are removed.

Abstract translation: 在具有至少一个使用两种不同光致抗蚀剂材料的电镀通孔的基板上形成电路。 将第一光致抗蚀剂施加在位于衬底上的导电层上，并显影以限定所需的导电电路图案。 将第二光致抗蚀剂层压到结构上并显影，使得第二光致抗蚀剂材料保留在通孔附近。 蚀刻导电层以提供期望的电路图案，并且去除第二和第一光致抗蚀剂的剩余部分。

公开(公告)号：US5751060A

公开(公告)日：1998-05-12

申请号：US795181

申请日：1997-02-04

Applicant: Eric Herman Laine ,  James Warren Wilson

Inventor： Eric Herman Laine ,  James Warren Wilson

IPC: H01L21/56 ,  H01L23/14 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L33/62 ,  H01L23/34 ,  H01L23/48 ,  H01L23/495

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/142 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L33/62

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may "fan out" to the lesser (and larger) density lines and/or pads of the other portion of the circuitry. The resulting package is also of a thin profile configuration and particularly adapted for being positioned on and electrically coupled to a PCB or the like substrate having conductors thereon.

公开(公告)号：US5661089A

公开(公告)日：1997-08-26

申请号：US638252

申请日：1996-04-26

Applicant: James Warren Wilson

Inventor： James Warren Wilson

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H05K3/28 ,  H05K3/42 ,  H01L21/60

CPC classification number: H05K1/0206 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/3735 ,  H05K1/0204 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/181 ,  H05K2201/09572 ,  H05K2201/10416 ,  H05K2203/049 ,  H05K3/284 ,  H05K3/42 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A semiconductor chip package and method of making same wherein the package comprises a ceramic substrate having two layers of thermally and electrically conductive material (e.g., copper) on opposing surfaces thereof, these layers thermally and electrically coupled by metal material located within holes provided in the ceramic. A semiconductor chip is mounted on one of these layers and the contact sites thereof electrically coupled to spaced circuitry which, in a preferred embodiment, is formed simultaneously with both thermally conductive layers. Coupling of the circuitry to an external substrate (e.g., printed circuit board) is preferably accomplished using metallic spring clips. These clips are preferably soldered in position. A preferred metal for being positioned within the hole(s) is solder, one example being 10:90 tin:lead solder. The package as produced herein may further include two quantities of a protective encapsulant material located substantially on the upper portions thereof to protect the chip and circuitry. The preferred means for coupling the chip to the circuitry is to use a wire bonding operation.

Abstract translation: 一种半导体芯片封装及其制造方法，其中封装包括在其相对表面上具有两层导热和导电材料（例如铜）的陶瓷基板，这些层由位于孔内的孔内的金属材料热和电耦合 陶瓷。 半导体芯片安装在这些层中的一个上，并且其接触位置电耦合到间隔电路，在优选实施例中，它们与两个导热层同时形成。 优选地，使用金属弹簧夹来实现电路与外部基板（例如，印刷电路板）的耦合。 这些夹子优选地被焊接就位。 用于定位在孔内的优选金属是焊料，一个例子是10:90锡：铅焊料。 本文生产的包装可以进一步包括两个量的基本上位于其上部的保护性密封材料，以保护芯片和电路。 将芯片耦合到电路的优选方法是使用引线键合操作。

公开(公告)号：US06989297B2

公开(公告)日：2006-01-24

申请号：US10926210

申请日：2004-08-25

Applicant: Robert David Sebesta ,  James Warren Wilson

Inventor： Robert David Sebesta ,  James Warren Wilson

IPC: H01L21/82 ,  H01L29/40

CPC classification number: H05K1/0265 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10–17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on-opposite sides of a substrate.

Abstract translation: 一种电子结构和相关的制造方法，其包括具有附接的电路元件的衬底和不同厚度的导电接合焊盘。 与垫厚相关的垫类别包括厚垫（17至50微米），中垫（10-17微米）和薄垫（3至10微米）。 使用厚焊盘将球栅阵列（BGA）耦合到具有BGA与电路卡的附接的基板。 介质垫可用于通过使用接口小的焊球将芯片倒装芯片连接到基板。 涂覆有镍 - 金层的薄铜焊盘可用于通过引线接口将芯片耦合到衬底。 电结构包括具有不同厚度的两个焊盘的电耦合，使得焊盘位于衬底的相同表面或衬底的相对侧上。

公开(公告)号：US06739048B2

公开(公告)日：2004-05-25

申请号：US09491755

申请日：2000-01-27

Applicant: Gerald Walter Jones ,  Ross William Keesler ,  Voya Rista Markovich ,  William John Rudik ,  James Warren Wilson ,  William Earl Wilson

Inventor： Gerald Walter Jones ,  Ross William Keesler ,  Voya Rista Markovich ,  William John Rudik ,  James Warren Wilson ,  William Earl Wilson

IPC: H01K310

CPC classification number: H05K3/388 ,  H01L21/4846 ,  H01L21/4857 ,  H05K3/0023 ,  H05K3/16 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1581 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Abstract translation: 提供了一种制造电路化结构的工艺。 该方法包括提供其上具有电路的有机基底的步骤; 在有机基板上施加电介质膜; 在电介质膜中形成微孔; 在电介质膜和微孔上溅射金属种子层; 在金属籽晶层上镀金属层; 并在其上形成电路图案。

公开(公告)号：US06730857B2

公开(公告)日：2004-05-04

申请号：US09804921

申请日：2001-03-13

Applicant: John Joseph Konrad ,  Jeffrey McKeveny ,  James Warren Wilson

Inventor： John Joseph Konrad ,  Jeffrey McKeveny ,  James Warren Wilson

IPC: H05K109

CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/184 ,  H05K3/388 ,  H05K3/4661 ,  H05K2203/072 ,  H05K2203/107 ,  H05K2203/1338 ,  Y10T29/49124

Abstract: Embedded flush circuitry features are fabricated by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a later of dielectric material.

Abstract translation: 通过在激光烧蚀沟槽的侧壁和底部提供导电种子层来制造嵌入式嵌入式电路特征，其特征在于将一层导电金属镀在种子层上并沉积以后的介电材料。

公开(公告)号：US6150716A

公开(公告)日：2000-11-21

申请号：US783775

申请日：1997-01-15

Applicant: Stephen Wesley MacQuarrie ,  Wayne Russell Storr ,  James Warren Wilson

Inventor： Stephen Wesley MacQuarrie ,  Wayne Russell Storr ,  James Warren Wilson

IPC: H01L21/56 ,  H01L23/14 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L33/62 ,  H01L23/34

CPC classification number: H01L23/293 ,  H01L21/563 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/32 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/85399 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L33/62 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections. Electrical leads extend from the connection pads on the chip carrier and are connected to corresponding pads on a circuit board or the like to provide I/O signals for the IC chip. In certain embodiments, additional heat sinks can be attached to the chip carrier and, also in certain embodiments, chips can be mounted on both sides of the chip carrier to increase the capacity of the chip carrier.