公开(公告)号：US20230317594A1

公开(公告)日：2023-10-05

申请号：US17710802

申请日：2022-03-31

申请人： Tao CHU ,  Minwoo JANG ,  Aurelia WANG ,  Conor P. PULS ,  Lin HU ,  Jaladhi MEHTA ,  Brian GREENE ,  Chung-Hsun LIN ,  Walid M. HAFEZ ,  Paul PACKAN

发明人： Tao CHU ,  Minwoo JANG ,  Aurelia WANG ,  Conor P. PULS ,  Lin HU ,  Jaladhi MEHTA ,  Brian GREENE ,  Chung-Hsun LIN ,  Walid M. HAFEZ ,  Paul PACKAN

IPC分类号： H01L23/522 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42392 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/0673

摘要： Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate and a transistor over the substrate. In an embodiment, the transistor comprises a source, a gate, and a drain. In an embodiment, the semiconductor device further comprises a first metal layer above the transistor, where the first metal layer comprises, a source metal coupled to the source, a drain metal coupled to the drain, and a gate metal coupled to the gate. In an embodiment, the source metal, the drain metal, and the gate metal are parallel conductive lines. In an embodiment, a backside via passes through the substrate, and a contact metal in the first metal layer is coupled to the backside via. In an embodiment, the contact metal is oriented orthogonal to the source metal.

公开(公告)号：US09570467B2

公开(公告)日：2017-02-14

申请号：US14641117

申请日：2015-03-06

申请人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

发明人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

摘要翻译： 描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。 例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。 第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。 第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。 第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。 半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。 第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。 第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

公开(公告)号：US20170005187A1

公开(公告)日：2017-01-05

申请号：US15100286

申请日：2014-01-24

申请人： Walid M. Hafez ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L29/74 ,  H01L29/66 ,  H01L29/417 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L29/74 ,  H01L21/2255 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/785

摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

摘要翻译： 公开了半导体器件，集成电路器件和方法的实施例。 在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍和第二鳍。 第一翅片可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，第三材料设置在第四材料和第二材料之间。 第一和第三材料可以由第一类型的非本征半导体形成，并且第二和第四材料可以由第二种不同类型的外在半导体形成。 第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一个物质连接。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20150187709A1

公开(公告)日：2015-07-02

申请号：US14142629

申请日：2013-12-27

申请人： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

发明人： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC分类号： H01L23/62 ,  H01L21/3205 ,  H01L21/02

CPC分类号： H01L23/62 ,  H01L21/0217 ,  H01L21/32055 ,  H01L23/5256 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。 在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。 隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。 隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140308785A1

公开(公告)日：2014-10-16

申请号：US14313678

申请日：2014-06-24

申请人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

发明人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L49/02

CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

公开(公告)号：US08618613B2

公开(公告)日：2013-12-31

申请号：US13077681

申请日：2011-03-31

申请人： Xianghong Tong ,  Zhanping Chen ,  Walid M. Hafez ,  Zhiyong Ma ,  Sarvesh H. Kulkarni ,  Kevin X. Zhang ,  Matthew B. Pedersen ,  Kevin D. Johnson

发明人： Xianghong Tong ,  Zhanping Chen ,  Walid M. Hafez ,  Zhiyong Ma ,  Sarvesh H. Kulkarni ,  Kevin X. Zhang ,  Matthew B. Pedersen ,  Kevin D. Johnson

IPC分类号： H01L27/11 ,  H01L21/02 ,  H01L23/52

CPC分类号： H01L23/5252 ,  H01L21/44 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

公开(公告)号：US20130224926A1

公开(公告)日：2013-08-29

申请号：US13857578

申请日：2013-04-05

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

公开(公告)号：US20110215422A1

公开(公告)日：2011-09-08

申请号：US13107783

申请日：2011-05-13

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L21/8238 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US10090304B2

公开(公告)日：2018-10-02

申请号：US14914614

申请日：2013-09-25

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Jeng-Ya D. Yeh ,  Hsu-Yu Chang ,  Neville Dias ,  Chanaka Munasinghe

发明人： Chia-Hong Jan ,  Walid M Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L Dias ,  Chanaka D Munasinghe

IPC分类号： H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

摘要： An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.

公开(公告)号：US20160211262A1

公开(公告)日：2016-07-21

申请号：US14914614

申请日：2013-09-25

申请人： Walid M. HAFEZ ,  Chia-Hong JAN ,  Jeng-Ya D. YEH ,  Hsu-Yu CHANG ,  Neville DIAS ,  Chanaka MUNASINGHE

发明人： CHIA-HONG JAN ,  WALID M HAFEZ ,  JENG-YA DAVID YEH ,  HSU-YU CHANG ,  NEVILLE L DIAS ,  CHANAKA D MUNASINGHE

IPC分类号： H01L27/092 ,  H01L21/225 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06

CPC分类号： H01L27/0924 ,  H01L21/2256 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66803 ,  H01L29/7851

摘要： An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.

摘要翻译： 沿着非平面半导体鳍片结构的一部分形成杂质源膜。 杂质源膜可以作为从源膜扩散到半导体鳍中而变得电活性的杂质源。 在一个实施例中，杂质源膜被布置成邻近鳍片的有源区域和衬底之间的亚鳍片区域的一部分的侧壁表面，并且比与有源区域更靠近衬底。 在另外的实施例中，杂质源膜可以提供掺杂源，其相对于形成P / N结的衬底的区域互补掺杂，所述P / N结是隔离结构的至少一部分，电绝缘活性鳍 区域。