公开(公告)号：US09646954B2

公开(公告)日：2017-05-09

申请号：US13085745

申请日：2011-04-13

申请人： Shih-Wei Liang ,  Yu-Wen Liu ,  Hsien-Wei Chen

发明人： Shih-Wei Liang ,  Yu-Wen Liu ,  Hsien-Wei Chen

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L25/065 ,  H01L21/66 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L22/34 ,  H01L23/522 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05572 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2224/05552

摘要： An integrated circuit system comprising a first integrated and at least one of a second integrated circuit, interposer or printed circuit board. The first integrated circuit further comprising a wiring stack, bond pads electrically connected to the wiring stack, and bump balls formed on the bond pads. First portions of the wiring stack and the bond pads form a functional circuit, and second portions of the wiring stack and the bond pads form a test circuit. A portion of the bump balls comprising dummy bump balls. The dummy bump balls electrically connected to the second portions of the wiring stack and the bond pads. The at least one of the second integrated circuit, interposer or printed circuit board forming a portion of the test circuit.

公开(公告)号：US08664768B2

公开(公告)日：2014-03-04

申请号：US13463474

申请日：2012-05-03

申请人： Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

发明人： Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/053 ,  H01L23/12

CPC分类号： H01L23/485 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/115 ,  H05K2201/068 ,  H05K2201/09781 ,  H05K2201/10378

摘要： A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

摘要翻译： 一种结构包括具有多个球的衬底，半导体芯片和电连接衬底和半导体芯片的插入器。 所述插入器包括第一侧，与所述第一侧相对的第二侧，至少一个第一排除区域，所述至少一个第一排除区域延伸穿过所述多个球的每个球上方的所述插入器，至少一个主动通孔，其从所述插入件的第一侧延伸到 其中所述至少一个活性通孔形成在所述至少一个第一排除区域的外部，并且其中在所述至少一个第一排除区域内没有形成活性通孔，以及至少一个虚拟通孔， 所述插入器的第一侧到所述插入件的第二侧，其中所述至少一个虚拟通孔形成在所述至少一个第一排除区域内。

公开(公告)号：US08624359B2

公开(公告)日：2014-01-07

申请号：US13253845

申请日：2011-10-05

申请人： Chung-Ying Yang ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

发明人： Chung-Ying Yang ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

IPC分类号： H01L23/544

CPC分类号： H01L23/3142 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76895 ,  H01L23/3114 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2224/05552

摘要： A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.

摘要翻译： 晶片级芯片级封装（WLCSP）包括具有接触焊盘的有源表面和侧表面的半导体器件。 模具覆盖半导体器件的侧表面。 RDL结构包括电连接到接触焊盘并在半导体器件的有源表面上延伸的第一PPI线。 UBM层形成在第一PPI线上并电连接到第一PPI线。 密封环结构围绕模具上的半导体器件的上周围延伸。 密封环结构包括在与第一PPI线和UBM层中的至少一个相同的高度上延伸的密封层。 制造WLCSP的方法包括通过在模制的半导体器件上同时形成互连线和密封层来形成再布线层压结构。

公开(公告)号：US08618827B2

公开(公告)日：2013-12-31

申请号：US12903984

申请日：2010-10-13

申请人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

摘要翻译： 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US20130140706A1

公开(公告)日：2013-06-06

申请号：US13312538

申请日：2011-12-06

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

摘要翻译： 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。

公开(公告)号：US20130093077A1

公开(公告)日：2013-04-18

申请号：US13272540

申请日：2011-10-13

申请人： Shih-Wei LIANG ,  Hsien-Wei CHEN ,  Ying-Ju CHEN ,  Tsung-Yuan YU ,  Mirng-Ji LII

发明人： Shih-Wei LIANG ,  Hsien-Wei CHEN ,  Ying-Ju CHEN ,  Tsung-Yuan YU ,  Mirng-Ji LII

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/11 ,  H01L21/76841 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

摘要翻译： 半导体器件包括依次形成在半导体衬底上的钝化层，第一保护层，互连层和第二保护层。 互连层具有暴露部分，其上形成有阻挡层和焊料凸块。 钝化层，第一保护层，互连层和第二保护层中的至少一个包括形成在导电焊盘区域外的区域中的至少一个槽。

公开(公告)号：US08994181B2

公开(公告)日：2015-03-31

申请号：US13212536

申请日：2011-08-18

申请人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

发明人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

IPC分类号： H01L23/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L23/291 ,  H01L23/3192 ,  H01L23/5226 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48681 ,  H01L2224/48684 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.

摘要翻译： 提供了形成接合焊盘结构的机理。 接合焊盘具有凹陷区域，该凹陷区域由接合焊盘下方的钝化层中的开口形成。 上钝化层至少覆盖接合焊盘的凹陷区域，以减少凹陷区域中图案化和/或蚀刻残留物的捕获。 结果，焊盘腐蚀的可能性降低。

公开(公告)号：US08901730B2

公开(公告)日：2014-12-02

申请号：US13463667

申请日：2012-05-03

申请人： Ming-Kai Liu ,  Shih-Wei Liang ,  Hsien-Wei Chen ,  Kai-Chiang Wu

发明人： Ming-Kai Liu ,  Shih-Wei Liang ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC分类号： H01L23/48

CPC分类号： H01L24/17 ,  H01L21/50 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/52 ,  H01L24/13 ,  H01L24/15 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81986 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805

摘要： Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

摘要翻译： 封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP设备通过使用顶部封装的相应连接器上的底部封装上的多个PoP连接器连接顶部封装和底部封装而形成。 PoP设备还包括多个虚拟连接器，其包含在底部封装中并且未连接到顶部封装中的任何相应的连接器。

公开(公告)号：US08871629B2

公开(公告)日：2014-10-28

申请号：US13291550

申请日：2011-11-08

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/14 ,  G06F2217/40 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1405 ,  H01L2224/14133 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/05552

摘要： In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls.

摘要翻译： 在提高半导体器件的球强度的方法中，接收要形成为半导体器件的电连接的多个连接球的球形图案。 该图案包括彼此交叉的多个列和行。 球排列在列和行的交点处。 在球形图案的区域中的球的布置被修改，使得该区域不包括孤立的球。

公开(公告)号：US08692378B2

公开(公告)日：2014-04-08

申请号：US13312538

申请日：2011-12-06

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC分类号： H01L23/34

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

摘要翻译： 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。