公开(公告)号：US20190252523A1

公开(公告)日：2019-08-15

申请号：US15896827

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen LIN ,  Qingjun ZHOU ,  Ying ZHANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/02538 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/7831

Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to form second mandrel structures comprising the hardmask material and the gap fill material and the substrate is etched using the second mandrel structures as a mask to form fin structures.

公开(公告)号：US20160307772A1

公开(公告)日：2016-10-20

申请号：US14968509

申请日：2015-12-14

Applicant: Applied Materials, Inc.

Inventor： Tom CHOI ,  Qingjun ZHOU ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/31155 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/3215 ,  H01L21/32155

Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.

Abstract translation: 本文所述的实施例涉及用于蚀刻衬底的方法。 图案化处理，例如双重图案化和四重图案化处理，可以受益于本文所述的实施例，其包括进行惰性等离子体处理以将离子注入到间隔物材料中，对间隔物材料的注入区域进行蚀刻处理，并重复 惰性等离子体处理和蚀刻工艺以形成主要平坦的顶部间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制诸如压力的各种处理参数以影响期望的间隔物轮廓。

公开(公告)号：US20150118822A1

公开(公告)日：2015-04-30

申请号：US14068312

申请日：2013-10-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Ying ZHANG ,  Hua CHUNG ,  Srinivas D. NEMANI ,  Ludovic GODET

IPC: H01L21/762 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。

公开(公告)号：US20190252187A1

公开(公告)日：2019-08-15

申请号：US16259585

申请日：2019-01-28

Applicant: Applied Materials, Inc.

Inventor： Yung-chen LIN ,  Qingjun ZHOU ,  Xinyu BAO ,  Ying ZHANG

IPC: H01L21/033 ,  H01L21/8234

Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second regions of the substrate and form second mandrel structures comprising the hardmask material and the gap fill material. Fin structures are deposited on the substrate using the second mandrel structures as a mask.

公开(公告)号：US20170229315A1

公开(公告)日：2017-08-10

申请号：US15415348

申请日：2017-01-25

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Qingjun ZHOU ,  Jonathan Sungehul KIM

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67207

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a substrate processing system is disclosed herein. The substrate processing system includes a transfer chamber and a plurality of process chambers coupled to the transfer chamber. The plurality of process chambers includes a first process chamber, a second process chamber, and a third process chamber. The first process chamber is configured to directionally modify a surface of a film stack formed on the substrate. The second process chamber is configured to deposit an etchant on the surface of the film stack. The third process chamber is configured to expose the film stack to a high-temperature sublimation process.

公开(公告)号：US20160079126A1

公开(公告)日：2016-03-17

申请号：US14864389

申请日：2015-09-24

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/31116 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US20170243754A1

公开(公告)日：2017-08-24

申请号：US15398011

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Aurelien TAVERNIER ,  Qingjun ZHOU ,  Tom CHOI ,  Yungchen LIN ,  Ying ZHANG ,  Olivier JOUBERT

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/3115

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/823431

Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.

公开(公告)号：US20160293438A1

公开(公告)日：2016-10-06

申请号：US15080117

申请日：2016-03-24

Applicant: Applied Materials, Inc.

Inventor： Qingjun ZHOU ,  Jungmin KO ,  Tom CHOI ,  Sean KANG ,  Jeremiah PENDER ,  Srinivas D. NEMANI ,  Ying ZHANG

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

公开(公告)号：US20160099178A1

公开(公告)日：2016-04-07

申请号：US14875013

申请日：2015-10-05

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/306

CPC classification number: H01L21/02507 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/8258

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US20150372119A1

公开(公告)日：2015-12-24

申请号：US14320590

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/324 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes performing an ion implantation process to dope dopants into a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer predominantly comprises a first type of atoms formed therein, the dopants including a second type of atoms into the suspended nanowire structure, oxidating surfaces of the multiple material layers, and converting the first type of atoms in the material layer to the second type of atoms from the dopants doped therein.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实例中，在衬底上形成纳米线结构的方法包括进行离子注入工艺以将掺杂剂掺杂到衬底上的悬浮的纳米线结构中，所述悬浮的纳米线包括在悬浮的纳米线结构中重复形成间隔关系的多个材料层 ，其中所述材料层主要包含在其中形成的第一类型的原子，所述掺杂剂包括到所述悬浮的纳米线结构中的第二类型的原子，所述多个材料层的氧化表面，以及将所述材料层中的所述第一类型的原子转化为 来自掺杂掺杂物的第二类型的原子。