公开(公告)号：US20220298625A1

公开(公告)日：2022-09-22

申请号：US17834633

申请日：2022-06-07

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC: C23C16/16 ,  H01L21/324 ,  H01L21/768 ,  C23C16/02 ,  C23C16/18 ,  H01L21/02 ,  H01L21/285 ,  C23C16/455 ,  C23C16/50

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US20200035489A1

公开(公告)日：2020-01-30

申请号：US16513301

申请日：2019-07-16

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Hua CHUNG

IPC: H01L21/02 ,  H01L21/306

Abstract: In an embodiment, a method of selectively depositing a silicon germanium material on a substrate is provided. The method includes positioning the substrate within a substrate processing chamber, the substrate having a dielectric material and a silicon containing single crystal thereon; maintaining the substrate at a temperature of about 450° C. or less; exposing the substrate to a process gas comprising: a silicon source gas, a germanium source gas, an etchant gas, a carrier gas, and at least one dopant source gas; and epitaxially and selectively depositing a first silicon germanium material on the substrate.

公开(公告)号：US20180211836A1

公开(公告)日：2018-07-26

申请号：US15652736

申请日：2017-07-18

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Yi-Chiau HUANG ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/02532 ,  H01L21/02057 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7378

Abstract: The present disclosure generally relates to a device having a thin, low-defect, fully-relaxed silicon germanium (SiGe) layer, and methods of manufacture thereof. The methods generally include depositing a silicon oxide layer on a silicon layer, patterning the silicon oxide layer, exposing the silicon oxide layer to an etchant to form one or more recesses in the silicon layer and one or more faceted silicon oxide caps, and epitaxially growing a silicon germanium layer in the one or more recesses and over an apex of the one or more faceted silicon oxide caps. The device generally includes a silicon layer having one or more recesses defining one or more vertical extensions, one or more faceted silicon oxide caps on the one or more vertical extensions, and a silicon germanium layer in the one or more recesses and extending over an apex of the one or more faceted silicon oxide caps.

公开(公告)号：US20180073162A1

公开(公告)日：2018-03-15

申请号：US15413534

申请日：2017-01-24

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: C30B25/08 ,  C30B25/12 ,  C30B25/10 ,  C30B25/14 ,  C30B29/40 ,  C23C16/30 ,  C23C16/48 ,  C23C16/56 ,  H01L21/67

CPC classification number: C30B25/08 ,  C23C16/301 ,  C23C16/4405 ,  C23C16/481 ,  C23C16/56 ,  C30B25/00 ,  C30B25/105 ,  C30B25/12 ,  C30B25/14 ,  C30B25/165 ,  C30B29/06 ,  C30B29/40 ,  C30B33/00 ,  C30B35/00 ,  H01L21/2252 ,  H01L21/30 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67253

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.

公开(公告)号：US20180047569A1

公开(公告)日：2018-02-15

申请号：US15795070

申请日：2017-10-26

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Hua CHUNG ,  Abhishek DUBE

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L29/66795

Abstract: Embodiments of the present disclosure generally relate to methods for trench filling of high quality epitaxial silicon-containing material without losing selectivity of growth to dielectrics such as silicon oxides and silicon nitrides. The methods include epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound. In one embodiment, the halogenated silicon compound includes chlorinated silane and halogenated germanium compound includes chlorinated germane.

公开(公告)号：US20180033872A1

公开(公告)日：2018-02-01

申请号：US15418128

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Errol Antonio C. SANCHEZ ,  Hua CHUNG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/66795 ,  C23C16/45523 ,  C23C16/45525 ,  C30B25/025 ,  C30B25/04 ,  C30B25/165 ,  C30B25/186 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/24 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.

公开(公告)号：US20170018427A1

公开(公告)日：2017-01-19

申请号：US15156870

申请日：2016-05-17

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau HUANG ,  Hua CHUNG ,  Abhishek DUBE

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L29/66795

Abstract: Embodiments of the present disclosure generally relate to methods for trench filling of high quality epitaxial silicon-containing material without losing selectivity of growth to dielectrics such as silicon oxides and silicon nitrides. The methods include epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound. In one embodiment, the halogenated silicon compound includes chlorinated silane and halogenated germanium compound includes chlorinated germane.

Abstract translation: 本公开的实施例一般涉及用于沟槽填充高质量外延含硅材料的方法，而不丧失生长对诸如氧化硅和氮化硅之类的电介质的选择性。 所述方法包括通过将沟槽暴露于包含卤化硅化合物和卤化锗化合物的气体混合物而在形成于电介质层中的沟槽内外延生长含硅材料。 在一个实施方案中，卤化硅化合物包括氯化硅烷，卤代锗化合物包括氯化锗烷。

公开(公告)号：US20160079126A1

公开(公告)日：2016-03-17

申请号：US14864389

申请日：2015-09-24

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/31116 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US20180277649A1

公开(公告)日：2018-09-27

申请号：US15933072

申请日：2018-03-22

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan YE ,  Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU ,  Satheesh KUPPURAO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/02546 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/67167 ,  H01L21/823431 ,  H01L21/8252

Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.

公开(公告)号：US20180190489A1

公开(公告)日：2018-07-05

申请号：US15661124

申请日：2017-07-27

Applicant: Applied Materials, Inc.

Inventor： Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG ,  Schubert S. CHU ,  Abhishek DUBE

IPC: H01L21/02 ,  H01L29/167 ,  H01L21/306 ,  C30B25/18 ,  C30B29/10 ,  C23C16/38

CPC classification number: H01L21/02639 ,  C23C16/0236 ,  C23C16/04 ,  C23C16/38 ,  C30B25/186 ,  C30B29/10 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02614 ,  H01L21/02661 ,  H01L21/30604 ,  H01L29/167

Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.