公开(公告)号：US06768212B2

公开(公告)日：2004-07-27

申请号：US10342989

申请日：2003-01-15

申请人： Akira Karashima ,  Margaret Simmons-Matthews ,  Sohichi Kadoguchi

发明人： Akira Karashima ,  Margaret Simmons-Matthews ,  Sohichi Kadoguchi

IPC分类号： H01L2348

CPC分类号： H01L23/49811 ,  H01L23/49513 ,  H01L23/49517 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/20752 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The stitch bond area is adjacent to said die attachment area on the substrate. Moreover, a stud bump is formed on the substrate for preventing the die attachment material from contacting the stitch bond area when a die is attached to the die attachment area. A method for manufacturing a semiconductor package according to the present invention also is disclosed.

摘要翻译： 根据本发明的半导体封装包括用于接收管芯附接材料的管芯附接区域和用于从管芯接收引线的缝合区域。 针迹结合区域与基底上的所述管芯附着区域相邻。 此外，在基板上形成柱状凸块，以防止当模具附接到模具安装区域时模具安装材料接触线圈接合区域。 本发明还公开了一种半导体封装的制造方法。

公开(公告)号：US06873059B2

公开(公告)日：2005-03-29

申请号：US10008049

申请日：2001-11-13

申请人： Masazumi Amagai ,  Akira Karashima

发明人： Masazumi Amagai ,  Akira Karashima

IPC分类号： H01L21/58 ,  H01L21/68 ,  H01L23/31 ,  H01L23/498 ,  H10L29/40

CPC分类号： H01L21/6836 ,  H01L23/3114 ,  H01L23/4985 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/05599 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.

摘要翻译： 一种半导体器件，包括具有有源和无源表面的半导体芯片，所述被动表面借助于多层复合材料粘附到基底膜上; 该复合材料包括具有第一表面和第二表面的金属箔，以及粘合层附着在这些表面的每一个上。 多层复合材料的平均模量大于在半导体器件中使用的封装模塑料的模量。 通过将复合材料应用于面朝上的芯片级装置，焊接点的应力降低，焊料疲劳寿命提高。

公开(公告)号：US06583483B2

公开(公告)日：2003-06-24

申请号：US09909340

申请日：2001-07-19

申请人： Kenji Masumoto ,  Mutsumi Masumoto ,  Akira Karashima

发明人： Kenji Masumoto ,  Mutsumi Masumoto ,  Akira Karashima

IPC分类号： H01L3100

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48486 ,  H01L2224/49107 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/4945 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

摘要： In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the insulated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.

摘要翻译： 在本发明的半导体器件10中，接合焊盘20以安装在绝缘基板12上的半导体芯片14的主表面上的交错图案排列。多个柱形突起堆叠在焊盘20a的位于 内部行，并且这些柱形凸块包括柱形凸起叠层28.导电线22将绝缘基板上的焊盘18与相应的焊盘20连接。焊丝的起始部分在焊盘上形成，其端部形成在焊盘处。 通过柱凸块28，内焊盘上的导线22a的端部处于比外焊盘上的导线22b的端部更高的位置，使得不会发生相邻导线接触的问题。

公开(公告)号：US06780749B2

公开(公告)日：2004-08-24

申请号：US10414847

申请日：2003-04-16

申请人： Kenji Masumoto ,  Mutsumi Masumoto ,  Akira Karashima

发明人： Kenji Masumoto ,  Mutsumi Masumoto ,  Akira Karashima

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48486 ,  H01L2224/49107 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/4945 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

摘要： In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the insulated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.

摘要翻译： 在本发明的半导体器件10中，接合焊盘20以安装在绝缘基板12上的半导体芯片14的主表面上的交错图案排列。多个柱形突起堆叠在焊盘20a的位于 内部行，并且这些柱形凸块包括柱形凸起叠层28.导电线22将绝缘基板上的焊盘18与相应的焊盘20连接。焊丝的起始部分在焊盘上形成，其端部形成在焊盘处。 通过柱凸块28，内焊盘上的导线22a的端部处于比外焊盘上的导线22b的端部更高的位置，使得不会发生相邻导线接触的问题。

公开(公告)号：US06225703B1

公开(公告)日：2001-05-01

申请号：US09350868

申请日：1999-07-09

申请人： Norito Umehara ,  Chikara Azuma ,  Akira Karashima

发明人： Norito Umehara ,  Chikara Azuma ,  Akira Karashima

IPC分类号： H01L2328

CPC分类号： H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The purpose of the present invention is to reduce the warpage of the semiconductor package caused by thermal contraction. According to the present invention, semiconductor device (9) has plate-shaped member (7) which is positioned on a surface of semiconductor chip (1) and is sealed together with semiconductor chip (1) with molding resin (8). Said plate-shaped member (7) has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By placing a plate-shaped member with a small linear expansion coefficient on semiconductor chip (1), it is possible to reduce the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip leads to substantial reduction in the thickness of the molding resin on the semiconductor chip. The pulling force due to contraction of the molding resin that leads to warping is proportional to the thickness of the molding resin. Consequently, by using semiconductor device (9) of the present invention that contains the aforementioned plate-shaped member, it is possible to reduce the warpage of the package to a very low level.

摘要翻译： 本发明的目的是减少由热收缩引起的半导体封装的翘曲。 根据本发明，半导体器件（9）具有位于半导体芯片（1）的表面上并与半导体芯片（1）一起用模塑树脂（8）密封的板状部件（7）。 所述板状部件（7）的线膨胀系数小于上述成形树脂的线膨胀系数。 通过在半导体芯片（1）上放置具有小线性膨胀系数的板状构件，可以减小半导体芯片的上侧的热收缩。 此外，半导体芯片上的板状构件的存在导致半导体芯片上的模塑树脂的厚度显着降低。 由于模制树脂的收缩导致翘曲的拉力与模制树脂的厚度成比例。 因此，通过使用包含上述板状部件的本发明的半导体装置（9），能够将包装的翘曲度降低到非常低的水平。

公开(公告)号：US20050127498A1

公开(公告)日：2005-06-16

申请号：US11050234

申请日：2005-02-03

申请人： Masazumi Amagai ,  Akira Karashima

发明人： Masazumi Amagai ,  Akira Karashima

IPC分类号： H01L21/58 ,  H01L21/68 ,  H01L23/31 ,  H01L23/498 ,  H01L23/34

CPC分类号： H01L21/6836 ,  H01L23/3114 ,  H01L23/4985 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/05599 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.

摘要翻译： 一种半导体器件，包括具有有源和无源表面的半导体芯片，所述被动表面借助于多层复合材料粘附到基底膜上; 该复合材料包括具有第一表面和第二表面的金属箔，以及粘合层附着在这些表面的每一个上。 多层复合材料的平均模量大于在半导体器件中使用的封装模塑料的模量。 通过将复合材料应用于面朝上的芯片级装置，焊接点的应力降低，焊料疲劳寿命提高。

公开(公告)号：US5920116A

公开(公告)日：1999-07-06

申请号：US757880

申请日：1996-11-27

申请人： Norito Umehara ,  Akira Karashima

发明人： Norito Umehara ,  Akira Karashima

IPC分类号： H01L23/50 ,  H01L23/495 ,  H01L23/28

CPC分类号： H01L23/49503 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/78301 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181

摘要： In semiconductor device fabrication, warping of the support pins must be prevented so that the semiconductor element can be properly positioned during the wire-bonding and resin-sealing processes. The invention provides a process in which a V-shaped groove 33, for example, is formed in the mounting pad 31 and the support pins 32, imparting rigidity to the support pins 32.

摘要翻译： 在半导体器件制造中，必须防止支撑销的翘曲，使得半导体元件可以在引线接合和树脂封装工艺期间被适当地定位。 本发明提供了一种方法，其中例如在安装垫31和支撑销32中形成V形凹槽33，赋予支撑销32刚性。

公开(公告)号：US4870474A

公开(公告)日：1989-09-26

申请号：US127721

申请日：1987-12-02

申请人： Akira Karashima

发明人： Akira Karashima

IPC分类号： H01L21/56 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L23/49544 ,  H01L2924/0002

摘要： A lead frame composed of an outer frame and inner lead frame portions formed as an integral frame wherein each lead frame portion directly joins the outer frame at some of the four corners of the lead frame portion with circuitous bridges interposed for fixation of the lead frame portion to the outer frame at each of the other corners.

摘要翻译： 一种引线框架，由外框架和形成为整体框架的内引线框架部分构成，其中每个引线框架部分在引线框架部分的四个角部的一部分处直接连接外框，其中插入有用于固定引线框架部分的迂回桥 到每个其他角落的外框。