利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.019 秒)

    Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
    2.
    发明授权
    Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies 有权
    用于堆叠模具组件的复原晶片的激光辅助切割

    公开(公告)号：US08575758B2

    公开(公告)日：2013-11-05

    申请号：US13197856

    申请日：2011-08-04

    申请人： Jeffrey Alan West ,  Margaret Simmons-Matthews ,  Raymundo M. Camenforte

    发明人： Jeffrey Alan West ,  Margaret Simmons-Matthews ,  Raymundo M. Camenforte

    IPC分类号： H01L23/498

    CPC分类号： H01L21/78 ,  H01L21/563 ,  H01L21/568 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

    摘要翻译： 一种形成堆叠管芯器件的方法包括将第一半导体管芯附着到晶片上以形成重构的晶片，然后将第二半导体管芯接合到第一半导体管芯上，以在晶片上形成多个单独堆叠的管芯器件。 支撑带附接到第二半导体管芯的底部。 切割胶带附着在晶片上。 在将切割带安装到预定的切割通道之前或之后，将该晶片激光照射，该切割线与第一半导体管芯之间的间隙对准，以在期望的切割通道机械地削弱晶片，但不切割穿过晶片。 将切割带拉动以将晶片切割成多个单个部分，以通过切割带形成附接到单个晶片部分的多个单独堆叠的裸片器件。 在切割之前移除支撑带。

    Semiconductor wafer with ditched scribe street
    3.
    发明申请
    Semiconductor wafer with ditched scribe street 审中-公开
    半导体晶圆与划痕街道

    公开(公告)号：US20050266661A1

    公开(公告)日：2005-12-01

    申请号：US10853812

    申请日：2004-05-26

    申请人： Lei Li ,  Vish Sundararaman ,  Margaret Simmons-Matthews

    发明人： Lei Li ,  Vish Sundararaman ,  Margaret Simmons-Matthews

    IPC分类号： H01L21/301 ,  H01L21/78

    CPC分类号： H01L21/78

    摘要： A semiconductor wafer (10) and associated methods are disclosed in which a plurality of semiconductor dice (14) include a semiconductor substrate (12) overlain by a plurality of upper layers (13) are provided with encompassing scribe streets (20) at the top surface (16) of the wafer (10) defined by inactive areas (18) between and circumscribing the dice (14). Ditches (22) in the scribe streets (20) extend from the top surface (16) to the substrate (12) for facilitating saw singulation of the dice (14).

    摘要翻译： 公开了一种半导体晶片（10）及其相关方法，其中包括多个上层（13）所覆盖的半导体衬底（12）的多个半导体晶片（14）在顶部设置有包围的划线（20） 所述晶片（10）的表面（16）由无源区域（18）限定并限定所述骰子（14）。 划线（20）中的沟槽（22）从上表面（16）延伸到基板（12），以便于骰子（14）的锯切。

    Through carrier dual side loop-back testing of TSV die after die attach to substrate
    4.
    发明授权
    Through carrier dual side loop-back testing of TSV die after die attach to substrate 有权
    通过载体双端回路测试TSV裸片裸片附着于基板上

    公开(公告)号：US08344749B2

    公开(公告)日：2013-01-01

    申请号：US12795376

    申请日：2010-06-07

    申请人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    发明人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2886 ,  G01R31/2896

    摘要： A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

    摘要翻译： 一种测试电子组件的方法，包括在衬底载体上附着到ML封装衬底上的分离的TSV芯片。 衬底载体包括用于允许探针接触耦合到TSV的前侧的封装衬底的底部上的BGA衬底焊盘的通孔。 TSV管芯底部的可接触的TSV尖端与顶侧耦合器接触，顶侧耦合器包括与TSV端头的至少一部分的布局匹配的耦合端子的图案，耦合到TSV端头的焊盘。 顶侧耦合器电连接成对的耦合端子以提供多个TSV回环路径。 BGA衬底焊盘与延伸穿过通孔的多个探针尖端接触以耦合到TSV的前侧。 在电子组件上执行电气测试以获得至少一个测试参数。

    THROUGH CARRIER DUAL SIDE LOOP-BACK TESTING OF TSV DIE AFTER DIE ATTACH TO SUBSTRATE
    8.
    发明申请
    THROUGH CARRIER DUAL SIDE LOOP-BACK TESTING OF TSV DIE AFTER DIE ATTACH TO SUBSTRATE 有权
    通过搬运到底板后的TSV DIE的运输双面环回测试

    公开(公告)号：US20110298488A1

    公开(公告)日：2011-12-08

    申请号：US12795376

    申请日：2010-06-07

    申请人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    发明人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Kenneth M. Butler ,  Margaret Simmons-Matthews

    IPC分类号： G01R31/02 ,  G01R1/067 ,  G01R31/26

    CPC分类号： G01R31/2886 ,  G01R31/2896

    摘要： A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

    摘要翻译： 一种测试电子组件的方法，包括在衬底载体上附着到ML封装衬底上的单独的TSV裸片。 衬底载体包括用于允许探针接触耦合到TSV的前侧的封装衬底的底部上的BGA衬底焊盘的通孔。 TSV管芯底部的可接触的TSV尖端与顶侧耦合器接触，顶侧耦合器包括匹配终端的图案，该图案匹配TSV尖端的至少一部分的布局或耦合到TSV尖端的焊盘。 顶侧耦合器电连接成对的耦合端子以提供多个TSV回环路径。 BGA衬底焊盘与延伸穿过通孔的多个探针尖端接触以耦合到TSV的前侧。 在电子组件上执行电气测试以获得至少一个测试参数。