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12 条记录 (耗时 0.02 秒)

    Top-exposed semiconductor package and the manufacturing method
    2.
    发明授权
    Top-exposed semiconductor package and the manufacturing method 有权
    顶露半导体封装及其制造方法

    公开(公告)号：US09245831B1

    公开(公告)日：2016-01-26

    申请号：US14533244

    申请日：2014-11-05

    申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

    发明人： Yan Huo ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Hongtao Gao

    IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

    CPC分类号： H01L23/49562 ,  H01L23/3121 ,  H01L23/49524 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2924/13055 ,  H01L2924/13091

    摘要： A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer located at one corner of the second surface. A source metal plate and a gate metal plate are attached on source metal layer and gate metal layer respectively. A molding layer covers lead frame, semiconductor chip, source metal plate and gate metal plate, where lead surface, top surfaces of source metal plate and gate metal plate are exposed from top surface of molding layer.

    摘要翻译： 半导体封装包括具有管芯焊盘和连接到管芯焊盘的多个引线的引线框架，其中每个引线具有平行于管芯焊盘的引线表面，并且是从管芯焊盘向上弯曲的连续延伸部。 半导体芯片安装在芯片上，其中覆盖芯片的第一表面的漏极金属层连接到裸片，并且源金属层和栅极金属层位于与第一表面相对的第二表面上，栅极金属层位于一个 第二面的角落。 源极金属板和栅极金属板分别附着在源极金属层和栅极金属层上。 成型层覆盖引线框架，半导体芯片，源金属板和栅极金属板，其中引线表面，源极金属板和栅极金属板的顶表面从成型层的顶表面露出。

    Wafer level chip scale package structure and manufacturing method thereof
    7.
    发明授权
    Wafer level chip scale package structure and manufacturing method thereof 有权

    公开(公告)号：US11062969B2

    公开(公告)日：2021-07-13

    申请号：US16261517

    申请日：2019-01-29

    申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

    发明人： Cheow Khoon Oh ,  Ming-Chen Lu ,  Xiaoming Sui ,  Bo Chen ,  Vincent Xue

    IPC分类号： H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

    摘要： A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

    WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190157174A1

    公开(公告)日：2019-05-23

    申请号：US16261517

    申请日：2019-01-29

    申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

    发明人： Cheow Khoon Oh ,  Ming-Chen Lu ,  Xiaoming Sui ,  Bo Chen ,  Vincent Xue

    IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78

    摘要： A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

    Wafer level chip scale package structure and manufacturing method thereof
    9.
    发明授权
    Wafer level chip scale package structure and manufacturing method thereof 有权

    公开(公告)号：US10242926B2

    公开(公告)日：2019-03-26

    申请号：US15197609

    申请日：2016-06-29

    申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

    发明人： Cheow Khoon Oh ,  Ming-Chen Lu ,  Xiaoming Sui ,  Bo Chen ,  Vincent Xue

    IPC分类号： H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683

    摘要： A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.