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1.
公开(公告)号:US10438910B2
公开(公告)日:2019-10-08
申请号:US15387016
申请日:2016-12-21
发明人: Bora Baloglu , Curtis Zwenger , Ron Huemoeller
IPC分类号: H01L21/00 , H01L23/00 , H01L25/00 , H01L25/10 , H01L25/065
摘要: A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.
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2.
公开(公告)号:US20190189599A1
公开(公告)日:2019-06-20
申请号:US15847242
申请日:2017-12-19
发明人: Bora Baloglu , Ron Huemoeller , Curtis Zwenger
IPC分类号: H01L25/10 , H01L23/367 , H01L23/373 , H01L23/538 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/552 , H01L23/00
CPC分类号: H01L25/105 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4882 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/3672 , H01L23/3675 , H01L23/3677 , H01L23/3736 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L23/552 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/13082 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/214 , H01L2224/32135 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/81005 , H01L2224/81203 , H01L2224/81224 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H01L2924/3511 , H01L2224/81 , H01L2924/014 , H01L2924/00014
摘要: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.
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公开(公告)号:US20180277394A1
公开(公告)日:2018-09-27
申请号:US15467794
申请日:2017-03-23
CPC分类号: H01L21/4857 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/3185 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/16 , H01L25/105 , H01L25/50 , H01L2221/68359 , H01L2224/16227 , H01L2225/1035 , H01L2225/1058
摘要: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
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公开(公告)号:US10008393B2
公开(公告)日:2018-06-26
申请号:US15041649
申请日:2016-02-11
发明人: Dong Jin Kim , Jin Han Kim , Won Chul Do Do , Jae Hun Bae Bae , Won Myoung Ki , Dong Hoon Han , Do Hyung Kim , Ji Hun Lee , Jun Hwan Park , Seung Nam Son , Hyun Cho , Curtis Zwenger
IPC分类号: H01L21/48 , H01L21/683 , H01L23/538 , H01L23/31 , H01L21/56 , H01L23/00 , H01L23/498
CPC分类号: H01L21/4857 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2221/68304 , H01L2221/68318 , H01L2221/68331 , H01L2221/68345 , H01L2221/68363 , H01L2224/1132 , H01L2224/131 , H01L2224/13294 , H01L2224/133 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81192 , H01L2224/81203 , H01L2224/81224 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81464 , H01L2224/81815 , H01L2224/8191 , H01L2224/81911 , H01L2224/81913 , H01L2224/81914 , H01L2224/83 , H01L2224/83005 , H01L2224/83104 , H01L2224/83192 , H01L2224/92 , H01L2224/9202 , H01L2224/92125 , H01L2224/97 , H01L2924/1421 , H01L2924/1433 , H01L2924/14335 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2224/81 , H01L2924/00014 , H01L2924/014 , H01L2924/00012
摘要: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
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公开(公告)号:US20170278810A1
公开(公告)日:2017-09-28
申请号:US15398845
申请日:2017-01-05
IPC分类号: H01L23/00 , H01L23/498 , H01L21/762 , H01L21/48 , H01L23/538
CPC分类号: H01L24/03 , H01L21/48 , H01L21/4853 , H01L21/6835 , H01L21/76251 , H01L23/13 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L25/105 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/13082 , H01L2224/13101 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/92125 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/00012 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要: Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.
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公开(公告)号:US10790161B2
公开(公告)日:2020-09-29
申请号:US15937423
申请日:2018-03-27
发明人: Bora Baloglu , Curtis Zwenger , Ronald Huemoeller
摘要: Electronic components and an electronic device comprising one or more of the electronic components, and a method of manufacturing the electronic components and an electronic device comprising one or more of the electronic components. As non-limiting examples, various aspects of this disclosure provide vertical interconnect components and various other vertical electronic components, and a method of manufacturing thereof, and an electronic device comprising one or more of the vertical interconnect components and various other vertical electronic components, and a method of manufacturing thereof.
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公开(公告)号:US20190237343A1
公开(公告)日:2019-08-01
申请号:US16378741
申请日:2019-04-09
IPC分类号: H01L21/48 , H01L23/00 , H01L21/56 , H01L25/00 , H01L23/538 , H01L23/31 , H01L21/683 , H01L25/10
摘要: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
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公开(公告)号:US20180308712A1
公开(公告)日:2018-10-25
申请号:US16017735
申请日:2018-06-25
发明人: Dong Jin Kim , Jin Han Kim , Won Chul Do Do , Jae Hun Bae Bae , Won Myoung Ki , Dong Hoon Han , Do Hyung Kim , Ji Hun Lee , Jun Hwan Park , Seung Nam Son , Hyun Cho , Curtis Zwenger
IPC分类号: H01L21/48 , H01L21/683 , H01L23/538 , H01L23/00 , H01L23/498 , H01L23/31 , H01L21/56
CPC分类号: H01L21/4857 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2221/68304 , H01L2221/68318 , H01L2221/68331 , H01L2221/68345 , H01L2221/68363 , H01L2224/1132 , H01L2224/131 , H01L2224/13294 , H01L2224/133 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81192 , H01L2224/81203 , H01L2224/81224 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81464 , H01L2224/81815 , H01L2224/8191 , H01L2224/81911 , H01L2224/81913 , H01L2224/81914 , H01L2224/83 , H01L2224/83005 , H01L2224/83104 , H01L2224/83192 , H01L2224/92 , H01L2224/9202 , H01L2224/92125 , H01L2224/97 , H01L2924/1421 , H01L2924/1433 , H01L2924/14335 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2224/81 , H01L2924/00014 , H01L2924/014 , H01L2924/00012
摘要: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
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公开(公告)号:US20180233641A1
公开(公告)日:2018-08-16
申请号:US15947245
申请日:2018-04-06
发明人: David Clark , Curtis Zwenger
CPC分类号: H01L33/58 , H01L24/00 , H01L33/44 , H01L33/62 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2924/15311 , H01L2924/18161
摘要: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that that comprises a transparent, translucent, non-opaque, or otherwise optically-transmissive, external surface.
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10.
公开(公告)号:US20180190514A1
公开(公告)日:2018-07-05
申请号:US15905602
申请日:2018-02-26
发明人: Bora Baloglu , Curtis Zwenger , Ronald Huemoeller
IPC分类号: H01L21/56 , H01L23/00 , H01L21/683
CPC分类号: H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/96 , H01L24/97 , H01L2221/68359 , H01L2221/68377 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/1319 , H01L2224/16227 , H01L2224/81002 , H01L2224/81005 , H01L2224/81203 , H01L2224/81815 , H01L2224/83005 , H01L2224/83102 , H01L2224/9202 , H01L2224/9211 , H01L2224/92125 , H01L2224/96 , H01L2224/97 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/014 , H01L2924/00014 , H01L2224/19 , H01L2924/0781 , H01L2224/83
摘要: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide methods of making an electronic device, and electronic devices made thereby, that comprise forming first and second encapsulating materials, followed by further processing and the removal of the entire second encapsulating material.
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