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公开(公告)号:US20130140713A1
公开(公告)日:2013-06-06
申请号:US13308742
申请日:2011-12-01
申请人: Chen-Hua Yu , Chien-Chia Chiu , Cheng-Chieh Hsieh
发明人: Chen-Hua Yu , Chien-Chia Chiu , Cheng-Chieh Hsieh
CPC分类号: H01L24/75 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L2224/04105 , H01L2224/11002 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/73267 , H01L2224/757 , H01L2224/75743 , H01L2224/7598 , H01L2224/81002 , H01L2224/81132 , H01L2224/81143 , H01L2224/81191 , H01L2224/95146 , H01L2224/96 , H01L2224/97 , H01L2924/10253 , H01L2224/81 , H01L2924/00012 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要: The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer.
摘要翻译: 本公开涉及一种用于将顶模快速且精确地对准和安装到插入器晶片上的方法。 该方法通过将疏水性自组装单层以限定与插入物晶片上的顶模的布置相关的顶模放置区的图案施加于载体晶片来进行。 将液体提供到顶部模具放置区域中,并且顶部模具被放置成与液体接触。 液体的表面张力通过产生导致顶模与顶模放置区重叠的力自动对准顶模。 然后消除液体,并将顶模固定到载体晶片上。 载体晶片结合到插入器晶片,使顶模与插入件接触。
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公开(公告)号:US08557631B2
公开(公告)日:2013-10-15
申请号:US13308742
申请日:2011-12-01
申请人: Chen-Hua Yu , Chien-Chia Chiu , Cheng-Chieh Hsieh
发明人: Chen-Hua Yu , Chien-Chia Chiu , Cheng-Chieh Hsieh
IPC分类号: H01L21/00
CPC分类号: H01L24/75 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L2224/04105 , H01L2224/11002 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/73267 , H01L2224/757 , H01L2224/75743 , H01L2224/7598 , H01L2224/81002 , H01L2224/81132 , H01L2224/81143 , H01L2224/81191 , H01L2224/95146 , H01L2224/96 , H01L2224/97 , H01L2924/10253 , H01L2224/81 , H01L2924/00012 , H01L2224/11 , H01L2924/014 , H01L2924/00
摘要: The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer.
摘要翻译: 本公开涉及一种用于将顶模快速且精确地对准和安装到插入器晶片上的方法。 该方法通过将疏水性自组装单层以限定与插入物晶片上的顶模的布置相关的顶模放置区的图案施加于载体晶片来进行。 将液体提供到顶部模具放置区域中,并且顶部模具被放置成与液体接触。 液体的表面张力通过产生导致顶模与顶模放置区重叠的力自动对准顶模。 然后消除液体,并将顶模固定到载体晶片上。 载体晶片结合到插入器晶片,使顶模与插入件接触。
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公开(公告)号:US08664760B2
公开(公告)日:2014-03-04
申请号:US13343582
申请日:2012-01-04
申请人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hao Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
CPC分类号: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00
摘要: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
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公开(公告)号:US08610285B2
公开(公告)日:2013-12-17
申请号:US13298046
申请日:2011-11-16
申请人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号: H01L23/498 , H01L21/768 , H01L23/48 , H01L29/40
CPC分类号: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00
摘要: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.
摘要翻译: 封装组件不含其中的有源器件。 封装部件包括衬底,衬底中的通孔,衬底上的顶部电介质层,以及在顶部电介质层的顶表面上方具有顶表面的金属柱。 金属柱电连接到通孔。 扩散阻挡层在金属支柱的上表面之上。 焊料帽设置在扩散阻挡层上。
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公开(公告)号:US20110210444A1
公开(公告)日:2011-09-01
申请号:US12813212
申请日:2010-06-10
申请人: Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
发明人: Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
IPC分类号: H01L23/538 , H01L21/60 , H01L23/488
CPC分类号: H01L25/50 , H01L23/13 , H01L23/3677 , H01L23/42 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/1532 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
摘要翻译: 提供了使用插入器的3D半导体封装。 在一个实施例中,提供了具有电耦合到插入器的第一侧的第一管芯的插入器和电耦合到插入件的第二侧的第二管芯。 插入器电耦合到诸如封装衬底,高密度互连,印刷电路板等的下面的衬底。 衬底具有腔,使得第二管芯位于腔内。 使用空腔可以允许使用更小的导电凸块,从而允许使用更多数量的导电凸块。 散热器可以放置在空腔内以帮助从第二模具散热。
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公开(公告)号:US20120306080A1
公开(公告)日:2012-12-06
申请号:US13298046
申请日:2011-11-16
申请人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Kuo-Ching Hsu , Cheng-Chieh Hsieh , Ying-Ching Shih , Po-Hao Tsai , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号: H01L23/52
CPC分类号: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00
摘要: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.
摘要翻译: 封装组件不含其中的有源器件。 封装部件包括衬底,衬底中的通孔,衬底上的顶部电介质层和在顶部电介质层的顶表面上方具有顶表面的金属柱。 金属柱电连接到通孔。 扩散阻挡层在金属支柱的上表面之上。 焊料帽设置在扩散阻挡层上。
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公开(公告)号:US20120306073A1
公开(公告)日:2012-12-06
申请号:US13343582
申请日:2012-01-04
申请人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Cheng-Chieh Hsieh , Kuo-Ching Hsu , Ying-Ching Shih , Po-Hoa Tsai , Chin-Fu Kao , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号: H01L23/485 , H01L21/768
CPC分类号: H01L24/11 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/04 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05073 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10145 , H01L2224/10156 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/13017 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/13578 , H01L2224/13686 , H01L2224/16058 , H01L2224/16145 , H01L2224/81193 , H01L2224/81815 , H01L2924/01322 , H01L2924/01327 , H01L2924/3651 , H01L2924/3841 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/049 , H01L2924/053 , H01L2924/00
摘要: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
摘要翻译: 一种器件包括具有顶表面的顶部电介质层。 金属柱在顶部介电层的顶表面上具有一部分。 在金属柱的侧壁上形成非润湿层,其中非润湿层不能熔化到熔融焊料上。 焊接区域设置在金属柱上并电耦合到金属柱。
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公开(公告)号:US08519537B2
公开(公告)日:2013-08-27
申请号:US12813212
申请日:2010-06-10
申请人: Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
发明人: Shin-Puu Jeng , Kim Hong Chen , Shang-Yun Hou , Chao-Wen Shih , Cheng-Chieh Hsieh , Chen-Hua Yu
IPC分类号: H01L23/13 , H01L23/538 , H01L23/488
CPC分类号: H01L25/50 , H01L23/13 , H01L23/3677 , H01L23/42 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/1532 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
摘要翻译: 提供了使用插入器的3D半导体封装。 在一个实施例中,提供了具有电耦合到插入器的第一侧的第一管芯的插入器和电耦合到插入件的第二侧的第二管芯。 插入器电耦合到诸如封装衬底,高密度互连,印刷电路板等的下面的衬底。 衬底具有腔,使得第二管芯位于腔内。 使用空腔可以允许使用更小的导电凸块,从而允许使用更多数量的导电凸块。 散热器可以放置在空腔内以帮助从第二模具散热。
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公开(公告)号:US20140015106A1
公开(公告)日:2014-01-16
申请号:US13546218
申请日:2012-07-11
申请人: Cheng-Chieh Hsieh , Way Lee Cheng , Shang-Yun Hou , Shin-Puu Jeng
发明人: Cheng-Chieh Hsieh , Way Lee Cheng , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号: H01L23/34
CPC分类号: H01L23/427 , H01L21/563 , H01L23/3675 , H01L23/3677 , H01L23/562 , H01L25/0657 , H01L2224/16 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06565 , H01L2225/06589
摘要: One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.
摘要翻译: 一个或多个热管与衬底一起使用,以便提供通过衬底的热量,其可以在衬底和封装中的一个或多个半导体芯片之间的界面处积聚。 在一个实施例中,热管可以位于与半导体芯片相对的一侧的衬底上,并且通孔衬底可以用于通过衬底散热。 在替代实施例中,热管可以位于与半导体芯片相同的衬底侧上,并且可以热连接到一个或多个半导体芯片。
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公开(公告)号:US20130270690A1
公开(公告)日:2013-10-17
申请号:US13445734
申请日:2012-04-12
申请人: Cheng-Chieh Hsieh , Jing-Cheng Lin
发明人: Cheng-Chieh Hsieh , Jing-Cheng Lin
CPC分类号: H01L23/473 , H01L21/4882 , H01L2924/0002 , H01L2924/00
摘要: A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer.
摘要翻译: 一种方法包括在集成散热器的表面上形成第一氧化物层,并且在翅片的顶表面上形成第二氧化物层,其中散热片是散热片的一部分。 集成散热器通过第一氧化物层与第二氧化物层的结合而结合到散热器。
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