公开(公告)号：US06815342B1

公开(公告)日：2004-11-09

申请号：US09996118

申请日：2001-11-27

申请人： Chuan-cheng Cheng ,  Sethuraman Lakshminarayanan ,  Peter J. Wright ,  Hong Ying

发明人： Chuan-cheng Cheng ,  Sethuraman Lakshminarayanan ,  Peter J. Wright ,  Hong Ying

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

摘要翻译： 本文描述了低电阻互连线及其制造方法。 IC制造工艺用于制造Al和Cu层的互连线。 Cu层比现有技术更薄，但与Al层结合时，聚集的Cu / Al电阻降低到与非常厚的Cu层相当的点，而没有额外的成本和产率问题 由于使用较厚的铜沉积引起。 用于记忆修复的保险丝也可以使用本发明教导的方法制造，只有该过程的变化很小。

公开(公告)号：US20070114667A1

公开(公告)日：2007-05-24

申请号：US11283219

申请日：2005-11-18

申请人： Hemanshu Bhatt ,  Dilip Vijay ,  Jayanthi Pallinti ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao

发明人： Hemanshu Bhatt ,  Dilip Vijay ,  Jayanthi Pallinti ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao

IPC分类号： H01L23/52

CPC分类号： H05K1/0271 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/107 ,  Y10T428/12396 ,  H01L2924/00014 ,  H01L2924/00

摘要： Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.

摘要翻译： 钝化整合方案和焊盘结构以减少应力梯度和/或改善焊盘中的Al和金线键之间存在的接触表面。 垫结构之一提供了形成在单个铝垫中的多个凹陷区域。 可以在铝垫下方设置氧化物台面。 另一个垫结构提供形成在单个铝垫中的单个凹陷区域，并且铝垫设置在铜焊盘和多个沟槽/通孔焊盘之上。 另一个衬垫结构提供形成在单个铝垫中的单个凹陷区域，并且铝垫设置在铜垫的一部分上方，使得铝垫和铜垫相对于彼此交错。

公开(公告)号：US07531442B2

公开(公告)日：2009-05-12

申请号：US11290087

申请日：2005-11-30

申请人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao ,  Peter Burke ,  Ramaswamy Ranganathan ,  Qwai Low

发明人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao ,  Peter Burke ,  Ramaswamy Ranganathan ,  Qwai Low

IPC分类号： H01L21/44

CPC分类号： H01L21/76801 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

摘要翻译： 减少或消除电线接合部件中IMC裂纹问题的不同方式，包括：更换为顶部，R1和R2的更多压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。 每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

公开(公告)号：US06555874B1

公开(公告)日：2003-04-29

申请号：US09649380

申请日：2000-08-28

申请人： Sheng Teng Hsu ,  Douglas James Tweet ,  Bruce Dale Ulrich ,  Hong Ying

发明人： Sheng Teng Hsu ,  Douglas James Tweet ,  Bruce Dale Ulrich ,  Hong Ying

IPC分类号： H01L310392

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7378

摘要： A semiconductor structure includes, on a SOI substrate, a CMOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.

摘要翻译： 半导体结构在SOI衬底上包括在衬底上形成的CMOS; 和形成在衬底上的SiGe HBT。 制造半导体结构的方法包括制备其上具有多个有源区的SOI衬底; 在第一有源区中在SOI衬底上形成CMOS; 以及在另一有源区的SOI衬底上形成SiGe HBT。

公开(公告)号：US07205673B1

公开(公告)日：2007-04-17

申请号：US11283044

申请日：2005-11-18

申请人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao

发明人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53219 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.

摘要翻译： 一种接合焊盘结构，其包括铝接合焊盘，其包括一个或多个掺杂剂，其有效地将IMC的生长控制到标称电平，尽管晶片中存在高拉伸应力。 例如，铝可以掺杂1-2原子％的Mg。 或者，可以使用Pd或Si，或者可以使用诸如Cu或Si的元素作为掺杂剂，以便降低晶片中的整体拉伸应力。 这可以控制IMC的异常生长，从而阻止IMC裂纹形成。 可以使用掺杂剂的组合来控制拉伸应力并且还稍微改变金 - 铝界面，从而实现均匀和薄的IMC形成。 这倾向于减少或消除否则在引线键合转移时会发生的任何空隙或裂纹。

公开(公告)号：US06716645B2

公开(公告)日：2004-04-06

申请号：US10319314

申请日：2002-12-12

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Hong Ying ,  Bruce D. Ulrich ,  Yanjun Ma

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Hong Ying ,  Bruce D. Ulrich ,  Yanjun Ma

IPC分类号： H01L2100

CPC分类号： H01L21/28291 ,  H01L29/516 ,  H01L29/78391

摘要： A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

摘要翻译： 用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2，HfO 2，Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物，以减少操作电压并增加存储窗口， 设备的可靠性。

公开(公告)号：US20070102812A1

公开(公告)日：2007-05-10

申请号：US11269275

申请日：2005-11-08

申请人： Sey-Shing Sun ,  Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Hong Ying ,  Chiyi Kao ,  Peter Burke

发明人： Sey-Shing Sun ,  Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Hong Ying ,  Chiyi Kao ,  Peter Burke

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 μm. Another possibility is provide an extra 0.6 μm aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 μm aluminum layer, followed by another barrier layer of 60 nm, another aluminum layer of 0.6 μm and another barrier layer of 60 nm.

摘要翻译： 一种衬垫结构和钝化方案，可在Cu / Low-K BEOL处理期间减少或消除后引线键合模具中的IMC裂纹。 可以在1.2μm铝层和铜之间提供厚120nm的阻挡层。 另一种可能性是有效地分离阻挡层，其中铝层设置在两个阻挡层之间。 阻挡层可以是60nm，而设置在阻挡层之间的铝层可以是0.6μm。 另一种可能性是在顶部阻挡层上提供额外的0.6μm的铝层。 另一种可能性是在最顶层的铝层上提供额外的阻挡层，使得在0.6μm的铝层上提供60nm的顶部阻挡层，接着是60nm的另一阻挡层，另一个为0.6的铝层 妈妈和60nm的另一阻挡层。

公开(公告)号：US06759252B2

公开(公告)日：2004-07-06

申请号：US10621850

申请日：2003-07-16

申请人： Fengyan Zhang ,  Sheng Teng Hsu ,  Hong Ying

发明人： Fengyan Zhang ,  Sheng Teng Hsu ,  Hong Ying

IPC分类号： H01L2102

CPC分类号： H01L28/55 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/67086 ,  H01L41/0533

摘要： A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

摘要翻译： 钝化层包括用于钝化铁电材料例如Pt / SBt / Ir-Ta-O器件的钛掺杂氧化铝层。 用于钝化铁电材料的钛掺杂氧化铝层具有减少的应力和改善的钝化性能，并且易于沉积并被氧化。 MFM结构中的钝化层在形成气体环境中抵抗器件退火过程中的击穿和剥离。

公开(公告)号：US06630702B2

公开(公告)日：2003-10-07

申请号：US09819546

申请日：2001-03-27

申请人： Fengyan Zhang ,  Sheng Teng Hsu ,  Hong Ying

发明人： Fengyan Zhang ,  Sheng Teng Hsu ,  Hong Ying

IPC分类号： H01L27108

CPC分类号： H01L28/55 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/67086 ,  H01L41/0533

摘要： A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir—Ta—O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

公开(公告)号：US06541385B2

公开(公告)日：2003-04-01

申请号：US09855393

申请日：2001-05-14

申请人： Hong Ying ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Hong Ying ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21302

CPC分类号： H01L21/02071 ,  C04B41/009 ,  C04B41/5346 ,  C04B41/91 ,  C04B2111/00844 ,  H01L21/32136 ,  H01L28/60 ,  C04B35/495

摘要： A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.