公开(公告)号：US07223687B1

公开(公告)日：2007-05-29

申请号：US11465873

申请日：2006-08-21

申请人： Chung W. Ho ,  Shih-Lian Cheng ,  Leo Shen

发明人： Chung W. Ho ,  Shih-Lian Cheng ,  Leo Shen

IPC分类号： H01L21/4763

CPC分类号： H05K3/4682 ,  H05K3/0058 ,  H05K3/0097 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49124 ,  Y10T29/49126

摘要： A method of fabricating a printed wiring board comprising the following steps is provided. A portion of each of two dielectric layers or metal layers bonds to both sides of a carrier plate, respectively. Two build-up wiring structures are respectively formed on the dielectric layers or the metal layers by a build-up process. The portions of the dielectric layers or metal layers bonded to the carrier plate are removed such that the dielectric layers or metal layers and the build-up wiring structures formed thereon are released from the carrier plate to form two printed wiring boards.

摘要翻译： 提供一种制造印刷电路板的方法，包括以下步骤。 两个电介质层或金属层中的每一个的一部分分别结合到载体板的两侧。 通过堆积工艺在电介质层或金属层上分别形成两个堆叠布线结构。 去除与载体板接合的电介质层或金属层的部分，使得形成在其上的电介质层或金属层和积聚线结构从载体板释放以形成两个印刷线路板。

公开(公告)号：US07540969B2

公开(公告)日：2009-06-02

申请号：US11565836

申请日：2006-12-01

申请人： Chung W. Ho ,  Leo Shen

发明人： Chung W. Ho ,  Leo Shen

IPC分类号： H01B13/00

CPC分类号： H01L23/142 ,  H01L23/49861 ,  H01L33/64 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K1/056 ,  H05K3/44 ,  H05K2201/0355 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0323 ,  H05K2203/0369 ,  H01L2924/00

摘要： A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself.

摘要翻译： 提供了一种高导热电路基板的制造工艺。 首先，提供金属芯基板，然后以不同的蚀刻速度蚀刻金属芯基板。 之后，在蚀刻后的金属芯基板的两面分别形成两层绝缘层。 此外，作为选择，分别在金属芯基板的两侧形成两个导电层，并且在绝缘层的顶部。 根据适合于产品的设计对导电层进行图案化。 由于作为上述制造工艺制造的高导热电路基板主要包括金属芯基板，所以有助于提高电路基板本身的热传导。

公开(公告)号：US20080257590A1

公开(公告)日：2008-10-23

申请号：US12034564

申请日：2008-02-20

申请人： Chung W. Ho ,  Leo Shen

发明人： Chung W. Ho ,  Leo Shen

IPC分类号： H05K1/03 ,  H01B13/00

CPC分类号： H01L23/142 ,  H01L23/49861 ,  H01L33/64 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K1/056 ,  H05K3/44 ,  H05K2201/0355 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0323 ,  H05K2203/0369 ,  H01L2924/00

摘要： A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself.

摘要翻译： 提供了一种高导热电路基板的制造工艺。 首先，提供金属芯基板，然后以不同的蚀刻速度蚀刻金属芯基板。 之后，在蚀刻后的金属芯基板的两面分别形成两层绝缘层。 此外，作为选择，分别在金属芯基板的两侧形成两个导电层，并且在绝缘层的顶部。 根据适合于产品的设计对导电层进行图案化。 由于作为上述制造工艺制造的高导热电路基板主要包括金属芯基板，所以有助于提高电路基板本身的热传导。

公开(公告)号：US20240243021A1

公开(公告)日：2024-07-18

申请号：US18413041

申请日：2024-01-16

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L23/13 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/15153 ,  H01L2924/15311

摘要： A package carrier includes a signal board, a power board and a connection layer. The signal board includes a plurality of first circuits. The power board includes a plurality of second circuits. A line width of each of the first circuits is less than a line width of each of the second circuits, and a first thickness of the signal board is less than a second thickness of the power board. The connection layer is disposed between the signal board and the power board, wherein the power board is electrically connected to the signal board through the connection layer.

公开(公告)号：US20120228015A1

公开(公告)日：2012-09-13

申请号：US13346738

申请日：2012-01-10

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H05K1/16 ,  H05K3/10 ,  H05K3/46 ,  H05K3/30 ,  H05K3/06 ,  H05K3/36 ,  H05K1/00 ,  H05K3/42

CPC分类号： H05K1/185 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/2518 ,  H01L2224/82005 ,  H01L2924/12042 ,  H05K1/116 ,  H05K3/0097 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09718 ,  H05K2203/1469 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A process of electronic structure is provided. First, a carrier board is provided, in which the carrier board has a first surface. Next, a first release layer is formed on the first surface of the carrier board. The first release layer has property of withstanding high-temperature and temporary adhesion capability and the first release layer entirely or mostly overlays the first surface. Then, a built-up structure is formed on the first release layer. Finally, a separating process is performed so that the built-up structure is separated from the carrier board to form an electronic structure.

摘要翻译： 提供电子结构的过程。 首先，提供载体板，其中承载板具有第一表面。 接下来，在载板的第一表面上形成第一释放层。 第一释放层具有耐高温和临时粘合能力的特性，并且第一释放层完全或大体上覆盖在第一表面上。 然后，在第一剥离层上形成积层结构。 最后，进行分离处理，使得积层结构与载体板分离以形成电子结构。

公开(公告)号：US06562656B1

公开(公告)日：2003-05-13

申请号：US09888258

申请日：2001-06-25

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L2144

CPC分类号： H01L21/4857 ,  H01L21/4853 ,  H01L21/52 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H05K3/20 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2924/00

摘要： The process of the invention starts with a metal panel, overlying the metal panel is created an interconnect substrate making use of BUM and thin film processing technology while the process of the invention enables the use of stacked vias and merged vias for the connection of the flip chip bumps. The process of the invention creates, for instance, two patterned layers on the surface of the metal panel whereby the metal panel is used as the ground terminal of the power supply. The first layer that is created on the surface of the metal panel can be the power supply layer (this layer can also be used for some fan-out interconnect lines), the second layer that is created on the surface of the metal panel is primarily used for (fan-out) interconnect lines. The flip chip bumps are, under the process of the invention, connected to the second layer of the interconnect substrate. Where the BGA balls also reside on the same surface as the flip chip bumps, the process of the invention does not require any additional structures such as a dam for the containment of insulating encapsulation material (underfill) that at times is provided around a perimeter of a well into which a flip chip is inserted, making the process of the invention most cost effective.

摘要翻译： 本发明的方法从金属面板开始，在金属面板的上方形成利用BUM和薄膜处理技术的互连衬底，而本发明的方法能够使用堆叠的通孔和合并的通孔来连接翻转 芯片颠簸 本发明的方法在金属板的表面上形成例如两个图案化层，由此金属板用作电源的接地端子。 在金属面板的表面上形成的第一层可以是电源层（该层也可以用于一些扇出的互连线），在金属面板的表面上形成的第二层主要是 用于（扇出）互连线。 在本发明的过程中，倒装芯片凸块连接到互连衬底的第二层。 当BGA球也位于与倒装芯片凸块相同的表面上时，本发明的方法不需要任何附加结构，例如用于容纳绝缘包封材料（底部填充物）的坝，其有时被设置在 其中插入倒装芯片的阱，使得本发明的方法最具成本效益。

公开(公告)号：US4812191A

公开(公告)日：1989-03-14

申请号：US55794

申请日：1987-06-01

申请人： Chung W. Ho ,  B. Y. Min

发明人： Chung W. Ho ,  B. Y. Min

IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/20 ,  H05K3/46 ,  B32B31/00 ,  B44C3/02

CPC分类号： H05K3/4682 ,  H01L21/4857 ,  H01L23/5383 ,  H05K3/467 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/0058 ,  H05K3/20 ,  Y10S156/922 ,  Y10T156/11

摘要： A method of fabricating a high density electrical interconnection member by forming a composite interconnection from metallic conductors on cured liquid polymer resin on substrate. The resin is cured at an elevated temperature to form a solid dielectric layer. Successive metallic and dielectric layers form an interconnection subassembly with the coefficient of thermal expansion of the substrate being less than the subassembly. The temperature of the subassembly is lowered placing it in tension. A support member is adhered to the exposed surface of the subassembly and the substrate removed. Multiple subassemblies can be joined together physically and electricaly to form a complex device for interconnecting a plurality of integrated circuit chips for high performance computer applications.

摘要翻译： 通过在基板上固化的液体聚合物树脂上的金属导体形成复合互连来制造高密度电互连部件的方法。 树脂在升高的温度下固化以形成固体介电层。 连续的金属和电介质层形成互连子组件，其中衬底的热膨胀系数小于子组件。 子组件的温度降低，使其处于张紧状态。 支撑构件粘附到子组件的暴露表面并移除衬底。 多个子组件可以物理和电气连接在一起以形成用于互连用于高性能计算机应用的多个集成电路芯片的复杂器件。

公开(公告)号：US11178774B1

公开(公告)日：2021-11-16

申请号：US17209236

申请日：2021-03-23

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H05K3/10 ,  H05K3/00

摘要： A manufacturing method of a circuit board is provided. A first carrier board included a substrate and a first conductive layer is provided, and the first conductive layer is located on a first surface of the substrate. A stainless steel layer is sputtered on the first conductive layer. An insulating layer is formed to cover a peripheral region of the stainless steel layer and expose a central region. A circuit structure layer is formed on the central region exposed by the insulating layer. A bottom surface of the circuit structure layer is connected to the first carrier board. A transferring procedure is performed to adhere a top surface of the circuit structure layer onto an adhesive layer of a second carrier board. The first carrier board is separated with the circuit structure layer to transfer the circuit structure layer onto the second carrier board, and expose the bottom surface of the circuit structure layer. The manufacturing method of the circuit board of the present invention is safer and simpler, may effectively reduce the manufacturing costs and improve the product yields.

公开(公告)号：US20090197364A1

公开(公告)日：2009-08-06

申请号：US12422428

申请日：2009-04-13

申请人： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

发明人： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

IPC分类号： H01L21/02 ,  H01L21/78

CPC分类号： H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

摘要翻译： 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度，并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

公开(公告)号：US06291268B1

公开(公告)日：2001-09-18

申请号：US09755568

申请日：2001-01-08

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L2150

CPC分类号： H01L21/4857 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

摘要： A new method is provided for the testing of complex, high density flip chip packages. A temporary electrical short is provided by a layer of metal for all the interconnect metal lines of the package, vias are created in a surface of the package for the connection of the flip chips to the package. These vias are plated using either copper or copper followed by nickel and gold. The process of plating requires uninterrupted electrical paths between the vias that are being plated and the layer of metal that provides a temporary electrical short. Where this uninterrupted electrical paths is not present, due to problems of poor via creation or problems of opens in the interconnect lines of the package, the vias will be improperly plated and can as a result be readily identified. The metal layer that has provided the common short between all interconnect lines of the package is now patterned and probed for problems of shorts or opens.

摘要翻译： 提供了一种用于测试复杂，高密度倒装芯片封装的新方法。 用于包装的所有互连金属线的金属层提供临时电短路，在封装的表面中形成通孔，用于将倒装芯片连接到封装。 这些通孔使用铜或铜，然后镀镍和金。 电镀的过程需要在正被镀覆的通孔和提供暂时的电短路的金属层之间的不间断的电路径。 在不存在该不间断电路的情况下，由于通孔产生不良或包装的互连线中的开路问题，通孔将被不适当地镀覆，因此可以容易地识别。 在封装的所有互连线之间提供了共同短路的金属层现在被图案化并被探测以产生短路或开路的问题。