公开(公告)号：US06465376B2

公开(公告)日：2002-10-15

申请号：US09377337

申请日：1999-08-18

申请人： Cyprian Emeka Uzoh ,  Daniel C. Edelstein ,  Andrew Simon

发明人： Cyprian Emeka Uzoh ,  Daniel C. Edelstein ,  Andrew Simon

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/76883 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S977/891 ,  H01L2924/00

摘要： A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.

摘要翻译： 微结构包括在基底上的铝，铜或其合金的导电层，其中该层包含至少约0.1微米的金属颗粒，以及沉积在金属表面的晶界中的阻挡材料及其制造方法。

公开(公告)号：US06251528B1

公开(公告)日：2001-06-26

申请号：US09004808

申请日：1998-01-09

申请人： Cyprian Emeka Uzoh ,  Daniel C. Edelstein

发明人： Cyprian Emeka Uzoh ,  Daniel C. Edelstein

IPC分类号： B32B1706

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1148 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/3025 ,  Y10T428/12299 ,  Y10T428/12361 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess.

摘要翻译： 一种在不使用掩模的情况下将第二金属直接镀在第一金属上的方法。 提供了包括至少一个金属特征和覆盖金属特征和基底的至少一个绝缘层的半导体基板。 在至少一个绝缘层中形成至少一个凹槽，从而暴露出金属特征的至少一部分。 在绝缘层和金属特征的暴露部分之上形成至少一个导电阻挡层。 在至少一个阻挡层上形成第一金属的电镀种子层。 在电镀种子层上沉积光致抗蚀剂层。 除去至少一个凹部外的光致抗蚀剂层和电镀种子层的部分。 残留在至少一个凹部中的光致抗蚀剂被去除。 将第二金属电镀到凹槽中的电镀种子层上。

公开(公告)号：US06297140B1

公开(公告)日：2001-10-02

申请号：US09389232

申请日：1999-09-03

申请人： Cyprian Emeka Uzoh ,  Daniel C. Edelstein

发明人： Cyprian Emeka Uzoh ,  Daniel C. Edelstein

IPC分类号： H01L2144

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1148 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/3025 ,  Y10T428/12299 ,  Y10T428/12361 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.

摘要翻译： 一种在不使用掩模的情况下将第二金属直接镀在第一金属上的方法。 提供了包括至少一个金属特征和覆盖金属特征和基底的至少一个绝缘层的半导体基板。 在至少一个绝缘层中形成至少一个凹槽，从而暴露出金属特征的至少一部分。 在绝缘层和金属特征的暴露部分之上形成至少一个导电阻挡层。 在至少一个阻挡层上形成第一金属的电镀种子层。 在电镀种子层上沉积光致抗蚀剂层。 除去光致抗蚀剂层的一部分和至少一个凹部外部的电镀种子层的部分。 残留在至少一个凹部中的光致抗蚀剂被去除。 第二金属被电镀到凹槽中的电镀种子层，使用阻挡层传导电流。

公开(公告)号：US06946716B2

公开(公告)日：2005-09-20

申请号：US10773434

申请日：2004-02-09

申请人： Panayotis Constantinou Andricacos ,  Harikilia Deligianni ,  John Owen Dukovic ,  Daniel C. Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth P. Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

发明人： Panayotis Constantinou Andricacos ,  Harikilia Deligianni ,  John Owen Dukovic ,  Daniel C. Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth P. Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L29/00

CPC分类号： C25D3/38 ,  C25D5/022 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76885

摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

摘要翻译： 描述了用于制造用于集成电路芯片的亚微米互连结构的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超量填充特征的能力是独一无二的，优于其他沉积方法。 以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US09245794B2

公开(公告)日：2016-01-26

申请号：US13614492

申请日：2012-09-13

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H05K1/09 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

摘要翻译： 提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。 本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。 在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

公开(公告)号：US09059251B2

公开(公告)日：2015-06-16

申请号：US13614524

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US08765602B2

公开(公告)日：2014-07-01

申请号：US13599256

申请日：2012-08-30

申请人： Thomas W. Dyer ,  Daniel C. Edelstein ,  Tze-man Ko ,  Andrew H. Simon ,  Wei-tsu Tseng

发明人： Thomas W. Dyer ,  Daniel C. Edelstein ,  Tze-man Ko ,  Andrew H. Simon ,  Wei-tsu Tseng

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

摘要翻译： 形成金属互连结构的方法包括在层间电介质（ILD）层内形成铜线; 用铜合金材料直接掺杂铜线的顶面; 并在ILD层和铜合金材料上形成介电层; 其中所述铜合金材料用于所述铜线和所述电介质层之间的粘合界面层。

公开(公告)号：US20140061915A1

公开(公告)日：2014-03-06

申请号：US13599295

申请日：2012-08-30

申请人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

发明人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76873 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

摘要翻译： 形成集成电路器件的方法包括在限定在衬底中的开口中形成扩散阻挡层; 在所述扩散阻挡层上形成高掺杂的铜合金种子层，所述铜合金种子层具有浓度大于0.5％原子的少数合金成分; 以及在所述铜合金晶种层上形成铜层，以限定所述集成电路器件的布线结构。

公开(公告)号：US20140024146A1

公开(公告)日：2014-01-23

申请号：US13565848

申请日：2012-08-03

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

公开(公告)号：US08564132B2

公开(公告)日：2013-10-22

申请号：US13211722

申请日：2011-08-17

申请人： Chih-Chao Yang ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Daniel C. Edelstein

IPC分类号： H01L23/482

CPC分类号： H01L21/76838 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76895

摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

摘要翻译： 提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。 这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。 在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。 然后形成与第一互连图案相邻但不连接的第二布线图案。 由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。