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49 条记录 (耗时 0.037 秒)

    Printed circuit board and method of manufacturing the same
    2.
    发明申请
    Printed circuit board and method of manufacturing the same 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：US20080053688A1

    公开(公告)日：2008-03-06

    申请号：US11896299

    申请日：2007-08-30

    申请人： Jun Park ,  Taehoon Kim ,  Dong Kim ,  Sam Her ,  Seung Kim

    发明人： Jun Park ,  Taehoon Kim ,  Dong Kim ,  Sam Her ,  Seung Kim

    IPC分类号： H05K1/00 ,  H05K3/10

    CPC分类号： H05K3/4644 ,  H05K1/024 ,  H05K3/108 ,  H05K3/205 ,  H05K3/381 ,  H05K3/388 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2203/092 ,  Y10T29/49155

    摘要： Disclosed herein are a thin printed circuit board, in which a pair of high-functional resin substrates having a permittivity ranging from 1.5 to 4.0, on one surface of each of which a circuit pattern is formed through ion-beam surface treatment, vapor deposition and electroplating, are layered with an insulating layer interposed therebetween, and a method of manufacturing the printed circuit board. The circuit patterns are positioned inside the substrates. Thereafter, external layers are formed through ion-beam surface treatment, vapor deposition and electroplating. According to the present invention, the adhesiveness between each of the substrates and a metal layer may be improved through the ion-beam surface treatment/vapor deposition. Furthermore, since the pair of resin substrates are layered with the insulating layer interposed therebetween, the circuit patterns may be disposed inside the pair of resin substrates, so that the total thickness of the substrate may be reduced, thereby realizing highly reliable fine circuits.

    摘要翻译： 这里公开了一种薄印刷电路板，其中一个表面具有介电常数范围为1.5至4.0的高功能树脂基板，每个表面上通过离子束表面处理形成电路图案，气相沉积和 电镀，其间插入有绝缘层，以及制造印刷电路板的方法。 电路图案位于基板内。 此后，通过离子束表面处理，气相沉积和电镀形成外层。 根据本发明，通过离子束表面处理/气相沉积，可以提高各基板与金属层的密合性。 此外，由于一对树脂基板被隔着绝缘层层叠，所以可以在一对树脂基板的内部设置电路图案，从而可以减小基板的总厚度，从而实现高可靠性的精细电路。

    Multiple level program verify in a memory device
    5.
    发明授权
    Multiple level program verify in a memory device 有权
    在存储设备中进行多级程序验证

    公开(公告)号：US08717823B2

    公开(公告)日：2014-05-06

    申请号：US13537150

    申请日：2012-06-29

    申请人： Taehoon Kim ,  Deping He ,  Jeffrey Alan Kessenich

    发明人： Taehoon Kim ,  Deping He ,  Jeffrey Alan Kessenich

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    摘要： A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

    摘要翻译： 一系列编程脉冲被施加到要编程的存储器单元。 在每个编程脉冲之后，在初始程序验证电压下将程序验证脉冲施加到存储单元。 初始程序验证电压是通过快速充电损耗电压增加的验证电压。 在编程脉冲达到某个参考电压或编程脉冲数达到脉冲计数阈值之后，从初始编程验证电压中减去快速充电损耗电压。

    Method of manufacturing build-up printed circuit board
    10.
    发明申请
    Method of manufacturing build-up printed circuit board 失效
    制造印刷电路板的方法

    公开(公告)号：US20070261234A1

    公开(公告)日：2007-11-15

    申请号：US11709215

    申请日：2007-02-22

    申请人： Jong Seok Song ,  Taehoon Kim ,  Dong Sun Kim ,  Hye Yeon Cha

    发明人： Jong Seok Song ,  Taehoon Kim ,  Dong Sun Kim ,  Hye Yeon Cha

    IPC分类号： H01K3/10 ,  H05K3/10 ,  H05K3/02

    CPC分类号： H05K3/381 ,  H05K3/108 ,  H05K3/146 ,  H05K3/4069 ,  H05K3/426 ,  H05K3/4602 ,  H05K2201/0959 ,  H05K2203/092 ,  H05K2203/1152 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： Disclosed is a method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.

    摘要翻译： 公开了一种积层印刷电路板的制造方法，其中通过使用干法形成芯层的金属种子层来实现包括芯层和外层的积层印刷电路板的电路 ，由离子束表面处理和真空沉积组成，代替常规的湿法，包括湿表面粗糙化处理和无电镀。 当在本发明的方法中用干法代替湿法时，电路层可以以环境友好的方式形成，并且可以制造包括芯层和外层的基片的所有电路层 通过半加成过程。 此外，可以提高树脂基板和金属层之间的剥离强度，从而实现高可靠性的精细电路。