公开(公告)号：US20030094700A1

公开(公告)日：2003-05-22

申请号：US10097815

申请日：2002-03-15

Applicant: Fujitsu Limited

Inventor： Yoshitaka Aiba ,  Hirohisa Matsuki ,  Mitsutaka Sato

IPC: H01L023/48

CPC classification number: H05K3/3436 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K2201/0129 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: There are provided a sealing insulating film that is formed on a substrate and melted at a first heating temperature to have a flowability, and external terminals that are formed on the substrate, and connected to other electronic device at a second heating temperature higher than the first heating temperature, and surrounded by the sealing insulating film.

Abstract translation: 提供了一种形成在基板上并在第一加热温度下熔化以具有流动性的密封绝缘膜，以及形成在基板上的外部端子，并且在比第一加热温度高的第二加热温度下连接到其它电子器件 加热温度，并被密封绝缘膜包围。

公开(公告)号：US20030151141A1

公开(公告)日：2003-08-14

申请号：US10374965

申请日：2003-02-28

Applicant: Fujitsu Limited

Inventor： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC: H01L023/48

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: There is provided a structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

公开(公告)号：US20030207574A1

公开(公告)日：2003-11-06

申请号：US10443837

申请日：2003-05-23

Applicant: Fujitsu Limited

Inventor： Yoshitaka Aiba ,  Mitsutaka Sato

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1067 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.

公开(公告)号：US20020121709A1

公开(公告)日：2002-09-05

申请号：US09895330

申请日：2001-07-02

Applicant: Fujitsu Limited

Inventor： Hirohisa Matsuki ,  Yutaka Makino ,  Masamitsu Ikumo ,  Mitsutaka Sato ,  Tetsuya Fujisawa ,  Yoshitaka Aiba

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/814 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/244 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: There is provided a structure in which a phosphorusnullnickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorusnullnickel layer, a nickelnulltin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.

Abstract translation: 提供了一种结构，其中磷镍层，含有比该磷 - 镍层高的​​磷或硼的富磷镍层，镍 - 锡合金层，富锡锡合金层和锡合金 焊料层依次形成在电极上。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。

公开(公告)号：US20020070440A1

公开(公告)日：2002-06-13

申请号：US09866660

申请日：2001-05-30

Applicant: Fujitsu Limited

Inventor： Yoshitaka Aiba ,  Mitsutaka Sato

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1067 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在具有电极焊盘的基板上形成布线以便将电极焊盘连接到安装端子的线形成步骤。 线形成步骤包括以下步骤：通过在其间提供粘合剂将金属箔施加到基底上; 将金属箔图案化成预定图案以形成布线; 并将布线与电极焊盘电连接。

公开(公告)号：US20020050639A1

公开(公告)日：2002-05-02

申请号：US10022572

申请日：2001-12-20

Applicant: Fujitsu Limited

Inventor： Yoshitaka Aiba ,  Mitsutaka Sato ,  Toshio Hamano

IPC: H01L023/34

CPC classification number: H01L23/49816 ,  H01L23/5382 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2224/05099

Abstract: A plurality of semiconductor chips are incorporated in a one-piece package so as to substantially increase a mounting area of a semiconductor device so that the semiconductor device can be provided with the projection electrodes having a structure which enable the semiconductor device to be mounted by a conventional surface mounting technique. A redistribution layer interconnects and integrally holds the plurality of semiconductor elements. A plurality of projection electrodes are provided on the redistribution layer for surface mounting. The plurality of semiconductor chips are rendered to be different kinds so that the plurality of different kinds of semiconductor chips together provide a complete function. The plurality of semiconductor chips may be rendered to be the same kind so as to reduce a mounting area of the semiconductor chips as a whole.

Abstract translation: 多个半导体芯片被结合在一体式封装中，从而大大增加了半导体器件的安装面积，使得半导体器件能够提供具有使半导体器件能够被安装在半导体器件上的结构的突起电极 常规表面贴装技术。 再分布层互连并整体地保持多个半导体元件。 在再分配层上设置多个投影电极用于表面安装。 将多个半导体芯片变为不同种类，使得多种不同种类的半导体芯片一起提供完整的功能。 可以使多个半导体芯片变得相同，从而整体上减小半导体芯片的安装面积。