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    Semiconductor integrated circuit device with built-in memories, and peripheral circuit which may be statically or dynamically operated
    1.
    发明授权
    Semiconductor integrated circuit device with built-in memories, and peripheral circuit which may be statically or dynamically operated 失效
    具有内置存储器的半导体集成电路器件和可以静态或动态操作的外围电路

    公开(公告)号：US4783764A

    公开(公告)日：1988-11-08

    申请号：US802198

    申请日：1985-11-25

    申请人： Fumio Tsuchiya ,  Kiyoshi Matsubara

    发明人： Fumio Tsuchiya ,  Kiyoshi Matsubara

    IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C16/102 ,  G11C16/08 ,  G11C16/26

    摘要： A data processing LSI constructing a microcomputer has an EPROM for changing a program. The EPROM can be accessed directly through the external terminals of the data processing LSI. The EPROM is statically operated when it is written with data by direct access. However, the statically operated EPROM consumes relatively high power. This power consumption by the EPROM is reduced by dynamically operating its read circuit, address decoder and so on. For example, the read circuit is constructed of a sense amplifier and a latch circuit, and the sense amplifier has its operation interrupted after the latch circuit has latched the read data. The address decoder is composed of a load MOSFET and address MOSFETs. The load MOSFET is caused to act as a precharge element in the dynamic operation and as an opertion current feeding element in the static operation.

    摘要翻译： 构成微型计算机的数据处理LSI具有用于改变程序的EPROM。 EPROM可以通过数据处理LSI的外部端子直接访问。 当通过直接访问写入数据时，EPROM是静态操作的。 然而，静态操作的EPROM消耗相对较高的功率。 通过动态地操作其读取电路，地址解码器等来减少EPROM的功耗。 例如，读取电路由读出放大器和锁存电路构成，并且在锁存电路锁存读取数据之后，读出放大器的操作中断。 地址解码器由负载MOSFET和地址MOSFET组成。 使负载MOSFET在动态运行中作为预充电元件，并作为静态工作中的操作电流馈电元件。

    Semiconductor integrated circuit device with built-in memories
    2.
    发明授权
    Semiconductor integrated circuit device with built-in memories 失效
    具有内置存储器的半导体集成电路器件

    公开(公告)号：US4908795A

    公开(公告)日：1990-03-13

    申请号：US255252

    申请日：1988-10-11

    申请人： Fumio Tsuchiya ,  Kiyoshi Matsubara

    发明人： Fumio Tsuchiya ,  Kiyoshi Matsubara

    IPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/26

    CPC分类号： G11C16/102 ,  G11C16/08 ,  G11C16/26

    摘要： A data processing LSI constructing a microcomputer has an EPROM for changing a program. The EPROM can be accessed directly through the external terminals of the data processing LSI. The EPROM is statically operated when it is written with data by direct access. However, the statically operated EPROM consumes relatively high power. This power consumption by the EPROM is reduced by dynamically operating its read circuit, address decoder and so on. For example, the read circuit is constructed of a sense amplifier and a latch circuit, and the sense amplifier has its operation interrupted after the latch circuit has latched the read data. The address decoder is composed of a load MOSFET and address MOSFETs. The load MOSFET is caused to act as a precharge element in the dynamic operation and as an operation current feeding element in the static operation.

    Semiconductor memory
    3.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5136546A

    公开(公告)日：1992-08-04

    申请号：US637798

    申请日：1991-01-07

    申请人： Minoru Fukuda ,  Hideaki Takahashi ,  June Sugiura ,  Fumio Tsuchiya ,  Toshimasa Kihara

    发明人： Minoru Fukuda ,  Hideaki Takahashi ,  June Sugiura ,  Fumio Tsuchiya ,  Toshimasa Kihara

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C2216/14

    摘要： An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converter parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.

    摘要翻译： 电可编程只读存储器配备有用于顺序地引入通过外部端子馈送的串联信号的锁存电路。 转换器包括顺序操作的开关元件和锁存电路，以将串联信号转换为并行信号。 这样的转换器并行信号通过地址解码器操作的选择开关元件同时写入存储器阵列。 根据这种方法，即使当并行信号动作的结果是一个写入操作相对较长时，也可以高速地进行对存储器阵列的写入操作。

    Semiconductor memory
    7.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4788665A

    公开(公告)日：1988-11-29

    申请号：US75986

    申请日：1987-07-21

    申请人： Minoru Fukuda ,  Hideaki Takahashi ,  June Sugiura ,  Fumio Tsuchiya ,  Toshimasa Kihara

    发明人： Minoru Fukuda ,  Hideaki Takahashi ,  June Sugiura ,  Fumio Tsuchiya ,  Toshimasa Kihara

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C8/00

    CPC分类号： G11C16/10 ,  G11C2216/14

    摘要： An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.

    摘要翻译： 电可编程只读存储器配备有用于顺序地引入通过外部端子馈送的串联信号的锁存电路。 转换器包括顺序操作的开关元件和锁存电路，以将串联信号转换为并行信号。 这样转换的并行信号通过地址译码器操作的选择开关元件同时写入存储器阵列。 根据这种方法，即使当并行信号动作的结果是一个写入操作相对较长时，也可以高速地进行对存储器阵列的写入操作。