公开(公告)号：US20100295043A1

公开(公告)日：2010-11-25

申请号：US12778123

申请日：2010-05-12

申请人： Bunji YASUMURA ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

发明人： Bunji YASUMURA ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

摘要翻译： 提供了能够防止半导体装置的最上层的保护膜的破裂的技术，提高了半导体装置的可靠性。 在半导体芯片的主表面上形成的接合焊盘为矩形，并且在每个接合焊盘上的保护膜中形成开口，使得保护膜在每个接合的引线接合区域中的重叠宽度 衬垫比每个焊盘的探针区域中的保护膜的重叠宽度宽。

公开(公告)号：US08946705B2

公开(公告)日：2015-02-03

申请号：US12778123

申请日：2010-05-12

申请人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

发明人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

摘要翻译： 提供了能够防止半导体装置的最上层的保护膜的破裂的技术，提高了半导体装置的可靠性。 在半导体芯片的主表面上形成的接合焊盘为矩形，并且在每个接合焊盘上的保护膜中形成开口，使得保护膜在每个接合的引线接合区域中的重叠宽度 衬垫比每个焊盘的探针区域中的保护膜的重叠宽度宽。

公开(公告)号：US08415199B2

公开(公告)日：2013-04-09

申请号：US13310261

申请日：2011-12-02

申请人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

发明人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/50

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US08101433B2

公开(公告)日：2012-01-24

申请号：US12413971

申请日：2009-03-30

申请人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

发明人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/66

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US20120077310A1

公开(公告)日：2012-03-29

申请号：US13310261

申请日：2011-12-02

申请人： Toshihiko AKIBA ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

发明人： Toshihiko AKIBA ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/50

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US20090243118A1

公开(公告)日：2009-10-01

申请号：US12413971

申请日：2009-03-30

申请人： Toshihiko AKIBA ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

发明人： Toshihiko AKIBA ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L23/48 ,  H01L21/66

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US07696723B2

公开(公告)日：2010-04-13

申请号：US10982479

申请日：2004-11-05

申请人： Masanao Sato

发明人： Masanao Sato

IPC分类号： H02J7/00

CPC分类号： H02J7/0047

摘要： A battery charger and a method of judging a charging condition of a secondary battery capable of judging precisely a charging condition of the secondary battery are provided. Charging conditions of the secondary battery are classified to four charging conditions depending on change of the voltage value of the secondary battery during charging operation, and one of these four charging conditions is displayed on the secondary battery by detecting the voltage value of the secondary battery at predetermined intervals.

摘要翻译： 提供一种电池充电器和判断能够准确判断二次电池的充电状态的二次电池的充电状态的方法。 根据充电操作期间二次电池的电压值的变化，将二次电池的充电条件分类为四个充电条件，并且通过检测二次电池的电压值在二次电池中显示这四个充电条件中的一个 预定间隔。

公开(公告)号：US20090121687A1

公开(公告)日：2009-05-14

申请号：US12290936

申请日：2008-11-05

申请人： Michihito Kobayashi ,  Masatsugu Honma ,  Yuichi Akita ,  Masanao Sato ,  Tohru Kurihara

发明人： Michihito Kobayashi ,  Masatsugu Honma ,  Yuichi Akita ,  Masanao Sato ,  Tohru Kurihara

IPC分类号： H02J7/00

CPC分类号： H01M10/44 ,  H01M10/46 ,  H02J7/0073 ,  Y02B40/90 ,  Y02E70/40

摘要： A charging apparatus for charging a plurality of batteries has at least two modes including a first mode and a second mode, in which amounts of electricity to charge the batteries are set with reference to a fully charged capacity of the batteries. The apparatus includes mode selection means for selecting either of the first mode and the second mode. The first mode is a mode in which the batteries are charged until the batteries reach a fully charged state. The second mode is a mode in which the charging of the batteries is stopped before the batteries reach the fully charged state.

摘要翻译： 用于对多个电池充电的充电装置具有至少两种模式，包括第一模式和第二模式，其中参照电池的完全充电容量来设定对电池充电的电量。 该装置包括用于选择第一模式和第二模式之一的模式选择装置。 第一模式是在电池达到完全充电状态之前将电池充电的模式。 第二模式是在电池达到完全充电状态之前停止电池的充电的模式。

公开(公告)号：US06493271B2

公开(公告)日：2002-12-10

申请号：US09987957

申请日：2001-11-16

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US6026020A

公开(公告)日：2000-02-15

申请号：US788198

申请日：1997-01-24

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F9/445 ,  G06F15/78 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11526 ,  G06F15/7814 ,  G06F15/7821 ,  G06F9/445 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C7/1045 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  H01L27/105 ,  Y02B60/185

摘要： A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the flash memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage from a corresponding one of plural source voltage control circuits, for flash erasing the memory cells in that memory block in an erasing operation. In accordance with another feature of the flash memory, a control register, included within a device and under the control of the CPU, is employed to control the erasing of data stored in one or more of the memory blocks, simultaneously.

摘要翻译： 具有中央处理单元（CPU）和闪速存储器的单芯片半导体集成电路器件，其存储要由CPU处理的数据，并且响应于通过地址访问来自CPU的指令，通过数据总线向CPU提供数据 总线。 闪存由多个存储块构成，每个存储块具有排列成行和列的多个电可编程非易失性存储单元，其中每个非易失性存储单元耦合到多个字线中的一个，多个字线中的一个 数据线的闪存。 所形成的存储器块可以通过不同的存储器容量来实现，包括通过控制与其相关联的存储器单元的行数或列数来实现。 每个存储块内的所有存储单元的源极连接到单个源极线，该源极线由多个源极电压控制电路中相应的一个源极电压控制电路的预定电压馈送，用于在擦除操作中闪存该存储器块中的存储器单元 。 根据闪速存储器的另一特征，使用包括在设备内并在CPU的控制下的控制寄存器来同时控制存储在一个或多个存储器块中的数据的擦除。