公开(公告)号：US08878259B2

公开(公告)日：2014-11-04

申请号：US13555383

申请日：2012-07-23

申请人： Harold J. Hovel ,  Qiang Huang ,  Xiaoyan Shao ,  James Vichiconti ,  George F. Walker

发明人： Harold J. Hovel ,  Qiang Huang ,  Xiaoyan Shao ,  James Vichiconti ,  George F. Walker

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L31/18 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/06 ,  C30B29/40 ,  C30B29/52 ,  C30B29/60 ,  C30B33/10 ,  H01L21/306 ,  H01L29/06 ,  H01L29/12 ,  H01L31/0352 ,  H01L33/20

CPC分类号： H01L31/18 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/06 ,  C30B29/40 ,  C30B29/52 ,  C30B29/60 ,  C30B29/605 ,  C30B33/10 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L31/0352 ,  H01L33/20

摘要： Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

摘要翻译： 在没有模板的情况下通过从两种或更多种半导体材料的层状结构中去除材料来制造分段半导体纳​​米线。 去除在层状结构的表面上的某些位置处发生，并且优选地沿着结晶轴的方向延伸，使得具有分段结构的纳米线保持在很少或不发生去除的位置。 不同片段之间的界面可以垂直于纳米线的纵向方向或与之相垂直。

公开(公告)号：US08665575B2

公开(公告)日：2014-03-04

申请号：US13166842

申请日：2011-06-23

申请人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer Krause ,  Zhengwen Li ,  Kevin S. Petrarca ,  Gerd Pfeiffer ,  Kevin Prettyman ,  Carl J. Radens ,  Brian C. Sapp

发明人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer Krause ,  Zhengwen Li ,  Kevin S. Petrarca ,  Gerd Pfeiffer ,  Kevin Prettyman ,  Carl J. Radens ,  Brian C. Sapp

IPC分类号： H02H5/04

CPC分类号： H02H7/20 ,  H01L31/02021 ,  H02H5/047 ,  Y02E10/50

摘要： A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).

摘要翻译： 具有在模块（10）内以串联和/或并联布置互连的多个太阳能电池（20）的光伏模块（10）装备有过热保护系统（30），用于抑制光伏模块（10）的损坏 涉及太阳能电池的缺陷（20）。 过热保护系统（30）包括热耦合到太阳能电池（20）的热传感器（32）。 热传感器（32）物理地集成在电连接到所述太阳能电池（20）的电开关（34,36,38）中。

公开(公告)号：US08653360B2

公开(公告)日：2014-02-18

申请号：US12849966

申请日：2010-08-04

申请人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L31/065 ,  H01L31/03765 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/548

摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.

摘要翻译： 光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层 半导体材料层。 第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体 第一和第二组成梯度半导体材料层中的材料层。 光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

公开(公告)号：US08569803B2

公开(公告)日：2013-10-29

申请号：US13572742

申请日：2012-08-13

申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC分类号： H01L29/76

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US08426236B2

公开(公告)日：2013-04-23

申请号：US12775939

申请日：2010-05-07

申请人： Cyril Cabral, Jr. ,  Harold J. Hovel ,  Xiaoyan Shao

发明人： Cyril Cabral, Jr. ,  Harold J. Hovel ,  Xiaoyan Shao

IPC分类号： H01L21/00

CPC分类号： H01L31/18 ,  H01L31/022425 ,  Y02E10/50

摘要： A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer.

摘要翻译： 包括硅衬底的太阳能电池的栅格堆叠结构，其中硅的正面被磷掺杂以形成n发射极，硅的背面用铝（Al）金属化丝网印刷; 作为抗反射涂层（ARC）的介电层，施加在硅上; 施加在前侧的掩模层以限定电介质层的栅格开口，其中施加蚀刻方法以打开未屏蔽的栅格区域; 施加到前侧的光诱导的镀镍或钴层与后侧Al金属化电接触; 通过镀镍（Ni）或钴（Co）的快速热退火形成的硅化物层; 电沉积在硅化物上的可选阻挡层; 电沉积在硅化物/阻挡膜层上的铜（Cu）层; 并且将薄的保护层化学施加或电沉积在Cu层的顶部上。

公开(公告)号：US20110212622A1

公开(公告)日：2011-09-01

申请号：US12714426

申请日：2010-02-26

申请人： Joel P. Desouza ,  Harold J. Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Joel P. Desouza ,  Harold J. Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/311

CPC分类号： H01L31/02363 ,  Y02E10/50

摘要： A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation.

摘要翻译： 描述了一种用于形成纹理Si表面的低成本方法，例如用于太阳能电池，其包括形成包含针孔的电介质层，通过针孔各向异性蚀刻以在Si表面中形成倒置的金字塔并除去电介质层，从而产生高光 捕获效率的入射辐射。

公开(公告)号：US07923628B2

公开(公告)日：2011-04-12

申请号：US12556335

申请日：2009-09-09

申请人： Hariklia Deligianni ,  Harold J. Hovel ,  Raman Vaidyanathan

发明人： Hariklia Deligianni ,  Harold J. Hovel ,  Raman Vaidyanathan

IPC分类号： H01L31/0216 ,  H01L31/18 ,  H01L21/3205 ,  H01L21/31

CPC分类号： H01L31/0749 ,  H01L31/0322 ,  Y02E10/541

摘要： A method of reducing the loss of elements of a photovoltaic thin film structure during an annealing process, includes depositing a thin film on a substrate, wherein the thin film includes a single chemical element or a chemical compound, coating the thin film with a protective layer to form a coated thin film structure, wherein the protective layer prevents part of the single chemical element or part of the chemical compound from escaping during an annealing process, and annealing the coated thin film structure to form a coated photovoltaic thin film structure, wherein the coated photovoltaic thin film retains the part of the single chemical element or the part of the chemical compound that is prevented from escaping during the annealing by the protective layer.

摘要翻译： 一种在退火工艺中减少光伏薄膜结构元件损耗的方法，包括在衬底上沉积薄膜，其中薄膜包括单一化学元素或化合物，用保护层涂覆薄膜 以形成涂覆的薄膜结构，其中所述保护层防止在退火过程期间所述单一化学元素或所述化学化合物的一部分的部分逸出，并且使所述涂覆的薄膜结构退火以形成涂覆的光伏薄膜结构，其中 涂覆的光伏薄膜保留在保护层退火期间防止单一化学元素或化学化合物部分逸出的部分。

公开(公告)号：US07897434B2

公开(公告)日：2011-03-01

申请号：US12189911

申请日：2008-08-12

申请人： Hans-Juergen Eickelmann ,  Michael Haag ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Markus Schmidt ,  Xiaoyan Shao ,  Steven Erik Steen

发明人： Hans-Juergen Eickelmann ,  Michael Haag ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Markus Schmidt ,  Xiaoyan Shao ,  Steven Erik Steen

IPC分类号： H01L21/00

CPC分类号： H01L31/068 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/022433 ,  H01L31/1804 ,  H01L31/1868 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

摘要翻译： 制造太阳能电池芯片的方法。 该方法包括在集成电路制造设备中创建用于使用集成电路晶片制造集成电路芯片的集成电路芯片工艺路线; 在集成电路制造设备中创建使用太阳能电池晶片制造太阳能电池的太阳能电池工艺路线; 将集成电路芯片晶片和太阳能电池晶片释放到集成电路制造设备的工具的工具队列中; 以及在用于处理集成电路晶片的集成电路制造设备的至少一些工具上处理太阳能电池晶片。 也是制造太阳能电池芯片的过程。

公开(公告)号：US20100221867A1

公开(公告)日：2010-09-02

申请号：US12436249

申请日：2009-05-06

申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

IPC分类号： H01L31/0376 ,  H01L21/762

CPC分类号： H01L31/03921 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02667 ,  H01L21/7624 ,  H01L21/76245 ,  H01L21/76262 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0465 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

摘要： A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate.

摘要翻译： 提供了一种用于制造SOI衬底的损耗成本方法。 该方法包括通过利用蒸发沉积工艺在衬底的半导体区域上形成一层p型掺杂的非晶态含Si层。 然后进行固相重结晶步骤，以将叠层内的非晶态含硅层转化为p型掺杂单晶含Si层的堆叠。 重结晶后，对单晶含Si层进行阳极氧化和至少氧化步骤以形成SOI衬底。 太阳能电池和/或其他半导体器件可以形成在本发明的SOI衬底的上表面上。

公开(公告)号：US20100037939A1

公开(公告)日：2010-02-18

申请号：US12189911

申请日：2008-08-12

申请人： Hans-Juergen Eickelmann ,  Michael Haag ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Markus Schmidt ,  Xiaoyan Shao ,  Steven Erik Steen

发明人： Hans-Juergen Eickelmann ,  Michael Haag ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Markus Schmidt ,  Xiaoyan Shao ,  Steven Erik Steen

IPC分类号： H01L31/00

CPC分类号： H01L31/068 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/022433 ,  H01L31/1804 ,  H01L31/1868 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

摘要翻译： 制造太阳能电池芯片的方法。 该方法包括在集成电路制造设备中创建用于使用集成电路晶片制造集成电路芯片的集成电路芯片工艺路线; 在集成电路制造设备中创建使用太阳能电池晶片制造太阳能电池的太阳能电池工艺路线; 将集成电路芯片晶片和太阳能电池晶片释放到集成电路制造设备的工具的工具队列中; 以及在用于处理集成电路晶片的集成电路制造设备的至少一些工具上处理太阳能电池晶片。 也是制造太阳能电池芯片的过程。