公开(公告)号：US20090317947A1

公开(公告)日：2009-12-24

申请号：US12461640

申请日：2009-08-19

申请人： Heung-kyu Kwon ,  Tae-Hun Kim ,  Sung-Yong Park

发明人： Heung-kyu Kwon ,  Tae-Hun Kim ,  Sung-Yong Park

IPC分类号： H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/4871 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package may include a heat sink. The heat sink may be disposed above and spaced apart from a substrate, which may support a semiconductor chip. The heat sink may have a hole. A liquid molding compound may be provided through the hole of the heat sink to form an encapsulant. The encapsulant may seal the semiconductor chip, leaving an upper portion of the heat sink exposed. A tape supporting the heat sink may be provided on the substrate. The tape may be removed after the encapsulant is provided.

摘要翻译： 半导体封装可以包括散热器。 散热器可以布置在可以支撑半导体芯片的衬底的上方并与之隔开。 散热器可能有一个孔。 可以通过散热器的孔提供液体模塑料以形成密封剂。 密封剂可以密封半导体芯片，留下散热器的上部。 可以在基板上设置支撑散热器的带。 在提供密封剂之后可以去除胶带。

公开(公告)号：US07541680B2

公开(公告)日：2009-06-02

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/12 ,  H01L23/48

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US20070045828A1

公开(公告)日：2007-03-01

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/34

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US07615415B2

公开(公告)日：2009-11-10

申请号：US11781377

申请日：2007-07-23

申请人： Heung-kyu Kwon ,  Tae-hun Kim ,  Su-chang Lee

发明人： Heung-kyu Kwon ,  Tae-hun Kim ,  Su-chang Lee

IPC分类号： H01L21/00

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.

摘要翻译： 通过提高接地性能并防止多芯片封装的湿度渗透到下半导体芯片中的可靠性降低，提供了具有提高的可靠性的垂直堆叠型多芯片封装。 垂直堆叠型多芯片封装包括具有其上安装有半导体芯片的印刷电路图案的有机基板。 第一半导体芯片安装在有机基板的芯片接合区域上，并通过第一导线与有机基板电连接。 在第一半导体芯片上形成金属加强件，并通过第一半导体芯片周围的第一接地单元与有机基板连接。 密封剂用于将金属加强件下方的第一半导体芯片密封。 尺寸大于第一半导体芯片的第二半导体芯片安装在金属加强件上并通过第二接地单元连接。 第二半导体芯片通过第二线连接到有机基板。 模具树脂密封第二半导体芯片，焊球与有机基板下方的焊球焊盘接合。

公开(公告)号：US07928555B2

公开(公告)日：2011-04-19

申请号：US11806589

申请日：2007-06-01

申请人： Tae-hun Kim ,  Heung-kyu Kwon

发明人： Tae-hun Kim ,  Heung-kyu Kwon

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/859 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

摘要翻译： 堆叠的半导体封装可以包括布线​​基板。 第一半导体芯片可以布置在布线基板上并且引线接合到布线基板。 可以在布线基板上布置插入件芯片，并将其连接到布线基板。 插入器芯片可以包括电连接的电路元件和接合焊盘。 第二半导体芯片可以设置在插入器芯片上并引线接合到插入器芯片。 第二半导体芯片可以通过插入器芯片电连接到布线基板。

公开(公告)号：US07868443B2

公开(公告)日：2011-01-11

申请号：US12603690

申请日：2009-10-22

申请人： Heung-kyu Kwon ,  Tae-hun Kim ,  Su-chang Lee

发明人： Heung-kyu Kwon ,  Tae-hun Kim ,  Su-chang Lee

IPC分类号： H01L23/02 ,  H01L23/29 ,  H01L23/10 ,  H01L23/48 ,  H01L23/34 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.

摘要翻译： 通过提高接地性能并防止多芯片封装的湿度渗透到下半导体芯片中的可靠性降低，提供了具有提高的可靠性的垂直堆叠型多芯片封装。 垂直堆叠型多芯片封装包括具有其上安装有半导体芯片的印刷电路图案的有机基板。 第一半导体芯片安装在有机基板的芯片接合区域上，并通过第一导线与有机基板电连接。 在第一半导体芯片上形成金属加强件，并通过第一半导体芯片周围的第一接地单元与有机基板连接。 密封剂用于将金属加强件下方的第一半导体芯片密封。 尺寸大于第一半导体芯片的第二半导体芯片安装在金属加强件上并通过第二接地单元连接。 第二半导体芯片通过第二线连接到有机基板。 模具树脂密封第二半导体芯片，焊球与有机基板下方的焊球焊盘接合。

公开(公告)号：US20080067659A1

公开(公告)日：2008-03-20

申请号：US11806589

申请日：2007-06-01

申请人： Tae-hun Kim ,  Heung-kyu Kwon

发明人： Tae-hun Kim ,  Heung-kyu Kwon

IPC分类号： H01L23/12 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/859 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

摘要翻译： 堆叠的半导体封装可以包括布线​​基板。 第一半导体芯片可以布置在布线基板上并且引线接合到布线基板。 可以在布线基板上布置插入件芯片，并将其连接到布线基板。 插入器芯片可以包括电连接的电路元件和接合焊盘。 第二半导体芯片可以设置在插入器芯片上并引线接合到插入器芯片。 第二半导体芯片可以通过插入器芯片电连接到布线基板。

公开(公告)号：US20110084380A1

公开(公告)日：2011-04-14

申请号：US12904502

申请日：2010-10-14

申请人： Heung-kyu Kwon ,  Hyung-Jun Lim ,  Byeong-yeon Cho

发明人： Heung-kyu Kwon ,  Hyung-Jun Lim ,  Byeong-yeon Cho

IPC分类号： H01L25/16

CPC分类号： H01L25/16 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.

摘要翻译： 其上安装有多个无源元件的半导体封装。 衬底包括第一表面和第二表面。 半导体芯片在基板的第一表面和第二表面之一上。 多个无源元件位于基板上。 多个无源元件包括多个第一无源元件和比多个第一无源元件更高的多个第二无源元件。 多个第一无源元件位于第一表面和第二表面中的至少一个上，并且多个第二无源元件中的至少两个位于第二表面上。

公开(公告)号：US20050200003A1

公开(公告)日：2005-09-15

申请号：US11033993

申请日：2005-01-13

申请人： Ki-myung Yoon ,  Heung-kyu Kwon ,  Hee-seok Lee

发明人： Ki-myung Yoon ,  Heung-kyu Kwon ,  Hee-seok Lee

IPC分类号： H01L25/07 ,  G11C11/34 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/60 ,  H01L23/00 ,  H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/488 ,  H01L23/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H05K5/00 ,  H05K5/04 ,  H05K5/06

CPC分类号： G11C16/10 ,  B82Y10/00 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multi-chip package may be provided which may include a substrate, on which multiple substrate bonding pads may be formed and under which multiple terminals may be formed, first and second semiconductor chips, which may be deposited on the substrate, and a spacer, which may be formed between the first and second semiconductor chips to have at least power and ground pads. The spacer may be used as passive element, and the first and second semiconductor chips and the power and ground pads of the spacer may be electrically connected. The pads of the semiconductor chip which may be deposited on the spacer may also be electrically connected to substrate bonding pads via the pads which may be formed on the spacer.

摘要翻译： 可以提供多芯片封装，其可以包括可以形成多个基板接合焊盘并且可以在其下形成多个端子的基板，可以沉积在基板上的第一和第二半导体芯片以及间隔件， 其可以形成在第一和第二半导体芯片之间以具有至少电源和接地焊盘。 间隔件可以用作无源元件，并且间隔件的第一和第二半导体芯片以及电源和接地焊盘可以电连接。 可以沉积在间隔物上的半导体芯片的焊盘也可以经由可以形成在间隔物上的焊盘电连接到衬底焊盘。

公开(公告)号：US08618671B2

公开(公告)日：2013-12-31

申请号：US12904502

申请日：2010-10-14

申请人： Heung-kyu Kwon ,  Hyung-Jun Lim ,  Byeong-yeon Cho

发明人： Heung-kyu Kwon ,  Hyung-Jun Lim ,  Byeong-yeon Cho

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00

CPC分类号： H01L25/16 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.

摘要翻译： 其上安装有多个无源元件的半导体封装。 衬底包括第一表面和第二表面。 半导体芯片在基板的第一表面和第二表面之一上。 多个无源元件位于基板上。 多个无源元件包括多个第一无源元件和比多个第一无源元件更高的多个第二无源元件。 多个第一无源元件位于第一表面和第二表面中的至少一个上，并且多个第二无源元件中的至少两个位于第二表面上。