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    SILICON WAFERS BY EPITAXIAL DEPOSITION
    4.
    发明申请
    SILICON WAFERS BY EPITAXIAL DEPOSITION 有权
    硅晶体通过外延沉积

    公开(公告)号：US20130032084A1

    公开(公告)日：2013-02-07

    申请号：US13483002

    申请日：2012-05-29

    申请人： Visweswaren Sivaramakrishnan ,  Tirunelveli S. Ravi ,  Quoc Vinh Truong ,  Jean R. Vatus ,  Visweswaren Sivaramakrishnan

    发明人： Visweswaren Sivaramakrishnan ,  Tirunelveli S. Ravi ,  Andrzej Kaszuba ,  Quoc Vinh Truong ,  Jean R. Vatus

    IPC分类号： C30B25/14 ,  C30B25/12

    CPC分类号： C30B25/14 ,  C30B25/105 ,  C30B25/12 ,  C30B25/165 ,  C30B25/20 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L31/1804

    摘要： A system for depositing thin single crystal silicon wafers by epitaxial deposition in a silicon precursor depletion mode with cross-flow deposition may include: a substrate carrier with low total heat capacity, high emissivity and small volume; a lamp module with rapid heat-up, efficient heat production, and spatial control over heating; and a manifold designed for cross-flow processing. Furthermore, the substrate carrier may include heat reflectors to control heat loss from the edges of the carrier and/or heat chokes to thermally isolate the carrier from the manifolds, allowing independent temperature control of the manifolds. The carrier and substrates may be configured for deposition on both sides of the substrates—the substrates having release layers on both sides and the carriers being configured to have equal process gas flow over both surfaces of the substrate. High volume may be addressed by a deposition system comprising multiple mini-batch reactors.

    摘要翻译： 通过在具有交叉流沉积的硅前体耗尽模式中通过外延沉积沉积薄单晶硅晶片的系统可以包括：具有低总热容量，高发射率和小体积的基板载体; 具有快速升温，高效热量生产和加热空间控制的灯模块; 以及设计用于交叉流处理的歧管。 此外，衬底载体可以包括热反射器，以控制从载体和/或热扼流器的边缘的热损失，以将载体与歧管热隔离，允许对歧管进行独立的温度控制。 载体和基底可以被配置用于在基底的两侧上沉积 - 在两侧上具有释放层的基底和载体构造成在基底的两个表面上具有相等的工艺气流。 高体积可以由包括多个微型间歇反应器的沉积系统来解决。

    High Throughput Multi-Wafer Epitaxial Reactor
    5.
    发明申请
    High Throughput Multi-Wafer Epitaxial Reactor 有权
    高通量多晶硅外延电抗器

    公开(公告)号：US20100215872A1

    公开(公告)日：2010-08-26

    申请号：US12392448

    申请日：2009-02-25

    申请人： Visweswaren Sivaramakrishnan ,  Kedarnath Sangam ,  Tirunelveli S. Ravi ,  Andrzej Kaszuba ,  Quoc Vinh Truong

    发明人： Visweswaren Sivaramakrishnan ,  Kedarnath Sangam ,  Tirunelveli S. Ravi ,  Andrzej Kaszuba ,  Quoc Vinh Truong

    IPC分类号： C23C16/56

    CPC分类号： C23C16/481 ,  C23C16/0209 ,  C23C16/455 ,  C23C16/4582 ,  C23C16/46 ,  C23C16/463 ,  C23C16/54 ,  C30B25/105 ,  C30B25/12 ,  C30B29/06

    摘要： An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize wall deposition. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases.

    摘要翻译： 公开了一种能够在多个晶片上同时沉积薄膜的外延反应器。 在沉积期间，许多晶片被包含在晶片套筒内，其包括间隔开的多个晶片承载板，以最小化处理体积。 工艺气体优先流入由一个或多个灯模块加热的晶片套筒的内部容积。 吹扫气体在反应器室内的晶片套筒外部流动，以最小化壁沉积。 此外，灯模组中各灯的照明顺序可以进一步提高晶片套筒内沉积速率变化的线性。 为了改善均匀性，工艺气体流动的方向可以在横流构型中变化。 将灯排序与多反应器系统中的交叉流处理相结合，可实现高通量沉积，具有良好的膜均匀性和有效利用工艺气体。

    Universal mid-frquency matching network
    8.
    发明申请
    Universal mid-frquency matching network 失效
    通用中频匹配网络

    公开(公告)号：US20050235916A1

    公开(公告)日：2005-10-27

    申请号：US10829520

    申请日：2004-04-21

    申请人： Eller Juco ,  Visweswaren Sivaramakrishnan ,  Mario Silvetti ,  Talex Sajoto

    发明人： Eller Juco ,  Visweswaren Sivaramakrishnan ,  Mario Silvetti ,  Talex Sajoto

    IPC分类号： C23C16/00 ,  C23C16/509 ,  H01J37/32

    CPC分类号： H01J37/32082 ,  C23C16/5096 ,  H01J37/32183

    摘要： A substrate processing system is provided with a processing chamber, an alternating voltage supply, and an impedance matching network. The processing chamber holds a substrate during processing and the alternating voltage supply is connected with the processing chamber to capacitively couple energy to a plasma formed within the processing chamber. The impedance matching network is coupled with the alternating voltage supply and has a variable resistive element and a variable reactive element, whose states respectively define distinct real and imaginary parts of an impedance.

    摘要翻译： 衬底处理系统设置有处理室，交流电压源和阻抗匹配网络。 处理室在处理期间保持基板，并且交流电压供应与处理室连接以将能量电容耦合到处理室内形成的等离子体。 阻抗匹配网络与交流电源耦合，并具有可变电阻元件和可变无功元件，其状态分别定义阻抗的不同实部和虚部。

    Process kit design for deposition chamber
    9.
    发明申请
    Process kit design for deposition chamber 审中-公开
    沉积室的工艺套件设计

    公开(公告)号：US20050150452A1

    公开(公告)日：2005-07-14

    申请号：US10757021

    申请日：2004-01-14

    申请人： Soovo Sen ,  Mark Fodor ,  Martin Seamons ,  Priya Kulkarni ,  Visweswaren Sivaramakrishnan ,  Sudha Rathi ,  Tsutomu Shimayama ,  Thomas Nowak ,  Wendy Yeh

    发明人： Soovo Sen ,  Mark Fodor ,  Martin Seamons ,  Priya Kulkarni ,  Visweswaren Sivaramakrishnan ,  Sudha Rathi ,  Tsutomu Shimayama ,  Thomas Nowak ,  Wendy Yeh

    IPC分类号： C23C16/44 ,  C30B25/14 ,  C23C16/00

    CPC分类号： C23C16/4412

    摘要： The present invention provides a process kit for a semiconductor processing chamber. The processing chamber is a vacuum processing chamber that includes a chamber body defining an interior processing region. The processing region receives a substrate for processing, and also supports equipment pieces of the process kit. The process kit includes a pumping liner configured to be placed within the processing region of the processing chamber, and a C-channel liner configured to be placed along an outer diameter of the pumping liner. The pumping liner and the C-channel liner have novel interlocking features designed to inhibit parasitic pumping of processing or cleaning gases from the processing region. The invention further provides a semiconductor processing chamber having an improved process kit, such as the kit described. In one arrangement, the chamber is a tandem processing chamber.

    摘要翻译： 本发明提供了一种用于半导体处理室的处理套件。 处理室是真空处理室，其包括限定内部处理区域的室主体。 处理区域接收用于处理的基板，并且还支持处理套件的设备件。 该处理套件包括构造成放置在处理室的处理区域内的泵送衬套，以及构造成沿着泵送衬套的外径放置的C形通道衬套。 泵送衬管和C通道衬管具有新颖的互锁特征，其设计用于抑制来自处理区域的处理或清洁气体的寄生泵送。 本发明还提供了一种具有改进的处理工具的半导体处理室，例如所述的套件。 在一种布置中，室是串联处理室。