公开(公告)号：US06987319B1

公开(公告)日：2006-01-17

申请号：US11006210

申请日：2004-12-06

Applicant: Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

Inventor： Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19041

Abstract: A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

Abstract translation: 晶片级芯片级封装包括具有平面顶表面和底表面的半导体管芯和在区域阵列中形成在顶表面处的多个金属焊盘。 第一保护层形成在半导体管芯的顶表面上，第一保护层具有多个用于允许金属焊盘向上打开的第一孔。 在所述第一保护层的表面上形成第二保护层，所述第二保护层具有多个第二孔，所述多个第二孔大于所述第一保护层的第一孔，并且过度相应地使所述金属垫和所述第一保护层 层暴露于半导体管芯的外部。 焊球与每个金属焊盘熔合，每个金属焊盘通过第一保护层的第一孔和第二保护层的第二孔向外开口。

公开(公告)号：US09048241B2

公开(公告)日：2015-06-02

申请号：US14063394

申请日：2013-10-25

Applicant: Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

Inventor： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

IPC: H01L23/02 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/83

Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

Abstract translation: 公开了一种利用再分配层耦合堆叠管芯的半导体器件，其可以包括第一半导体管芯，其具有包括接合焊盘的第一表面，与第一表面相对的第二表面以及第一和第二表面之间的倾斜侧表面， 第一个模具的截面形状为梯形。 具有第一表面的第二半导体管芯可以结合到第一管芯的第二表面，其中第二管芯的第一表面可以包括接合焊盘。 钝化层可以形成在第一模具的第一表面和倾斜的侧表面上以及第二模具的第一表面上。 可以在钝化层上形成再分配层，电耦合第一和第二裸片上的接合焊盘。 导电柱可以从第二管芯上的焊盘延伸到第二再分布层。

公开(公告)号：US09504525B2

公开(公告)日：2016-11-29

申请号：US14941657

申请日：2015-11-15

Applicant: In Bae Park

Inventor： In Bae Park

IPC: A61B18/22 ,  A61B18/00 ,  A61B18/20

CPC classification number: A61B18/22 ,  A61B2018/00196 ,  A61B2018/202 ,  A61B2018/2244 ,  A61B2018/225

Abstract: The present invention relates generally to a handpiece laser treatment apparatus for treating an affected area by irradiating lasers thereto. More particularly, the present invention relates to a handpiece laser treatment apparatus capable of adjusting the drawn length of an optical fiber in which laser is irradiated. The handpiece laser treatment apparatus capable of adjusting the length of optical fiber according to the present invention comprises: a laser module for generating a laser; an optical fiber that is connected to the laser module so that the laser is irradiated to the outside; a main body in which the laser module is inserted and disposed in the inside and the optical fiber is projected forwardly; and a slider for adjusting the length of the optical fiber which is projected in front of the body.

Abstract translation: 本发明一般涉及一种通过向其照射激光来治疗受影响区域的手持式激光治疗装置。 更具体地，本发明涉及一种能够调节照射激光的光纤的拉伸长度的手持式激光治疗装置。 根据本发明的能够调节光纤长度的手持式激光治疗装置包括：用于产生激光的激光模块; 连接到激光模块以使激光照射到外部的光纤; 其中激光模块插入并设置在内部并且光纤向前突出的主体; 以及用于调节投影在身体前方的光纤的长度的滑块。

公开(公告)号：US20150014830A1

公开(公告)日：2015-01-15

申请号：US14063394

申请日：2013-10-25

Applicant: Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

Inventor： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Won Chul Do ,  Pil Je Sung ,  Jin Hee Park ,  Do Hyung Kim ,  In Bae Park ,  Chang Min Lee ,  Yong Song ,  SungGeun Kang

IPC: H01L23/538 ,  H01L25/00

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/83

Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

Abstract translation: 公开了一种利用再分配层耦合堆叠管芯的半导体器件，其可以包括第一半导体管芯，其具有包括接合焊盘的第一表面，与第一表面相对的第二表面以及第一和第二表面之间的倾斜侧表面， 第一个模具的截面形状为梯形。 具有第一表面的第二半导体管芯可以结合到第一管芯的第二表面，其中第二管芯的第一表面可以包括接合焊盘。 钝化层可以形成在第一模具的第一表面和倾斜的侧表面上以及第二模具的第一表面上。 可以在钝化层上形成再分配层，电耦合第一和第二裸片上的接合焊盘。 导电柱可以从第二管芯上的焊盘延伸到第二再分布层。

公开(公告)号：US08362612B1

公开(公告)日：2013-01-29

申请号：US12728119

申请日：2010-03-19

Applicant: Jong Sik Paek ,  Eun Sook Sohn ,  In Bae Park ,  Won Chul Do ,  Glenn A. Rinne

Inventor： Jong Sik Paek ,  Eun Sook Sohn ,  In Bae Park ,  Won Chul Do ,  Glenn A. Rinne

IPC: H01L21/00

CPC classification number: H01L21/76885 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

Abstract translation: 公开了一种半导体器件及其制造方法。 在半导体管芯上形成第一绝缘层，在第一绝缘层上形成与接合焊盘电连接的再分配层，第二绝缘层覆盖再分布层。 第二绝缘层由便宜的非感光材料制成。 因此，可以降低半导体器件的制造成本。

公开(公告)号：US09748154B1

公开(公告)日：2017-08-29

申请号：US12939588

申请日：2010-11-04

Applicant: Boo Yang Jung ,  Jong Sik Paek ,  Choon Heung Lee ,  In Bae Park ,  Sang Won Kim ,  Sung Kyu Kim ,  Sang Gyu Lee

Inventor： Boo Yang Jung ,  Jong Sik Paek ,  Choon Heung Lee ,  In Bae Park ,  Sang Won Kim ,  Sung Kyu Kim ,  Sang Gyu Lee

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L23/00 ,  H01L23/3135 ,  H01L23/522 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/15172 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

公开(公告)号：US08446017B2

公开(公告)日：2013-05-21

申请号：US12562387

申请日：2009-09-18

Applicant: Jong Sik Paek ,  In Bae Park ,  Chang Deok Lee

Inventor： Jong Sik Paek ,  In Bae Park ,  Chang Deok Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/221 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/82106 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/83

Abstract: A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.

Abstract translation: 公开了一种可堆叠的晶片级封装及其制造方法。 在可堆叠晶片级封装中，接合焊盘（或再分配层）被布置在底部半导体管芯上，并且金属柱形成在位于底部半导体管芯的边缘周围的一些接合焊盘上。 顶部半导体管芯电连接到其上未形成金属柱的其它接合焊盘，通过导电凸块定位在底部半导体管芯的中心附近。 金属柱和顶部半导体管芯由密封剂封装。 电连接到金属柱的多个互连图案形成在密封剂的表面上。 焊球附接到互连图案。 由于这种堆叠结构，晶片级封装的厚度和占地面积减小。 因此，晶片级封装非常适合于移动应用。

公开(公告)号：US06841874B1

公开(公告)日：2005-01-11

申请号：US10285978

申请日：2002-11-01

Applicant: Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

Inventor： Jong Sik Paek ,  In Bae Park ,  Seong Min Seo

IPC: H01L23/31 ,  H01L23/485

CPC classification number: H01L24/03 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19041

Abstract: A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

Abstract translation: 晶片级芯片级封装包括具有平面顶表面和底表面的半导体管芯和在区域阵列中形成在顶表面处的多个金属焊盘。 第一保护层形成在半导体管芯的顶表面上，第一保护层具有多个用于允许金属焊盘向上打开的第一孔。 在所述第一保护层的表面上形成第二保护层，所述第二保护层具有多个第二孔，所述多个第二孔大于所述第一保护层的第一孔，并且过度相应地使所述金属垫和所述第一保护层 层暴露于半导体管芯的外部。 焊球与每个金属焊盘熔合，每个金属焊盘通过第一保护层的第一孔和第二保护层的第二孔向外开口。