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公开(公告)号:US07794820B2
公开(公告)日:2010-09-14
申请号:US11878165
申请日:2007-07-20
Applicant: Dong Sun Kim , Taehoon Kim , Jong Seok Song , Sam Jin Her , Jun Heyoung Park
Inventor: Dong Sun Kim , Taehoon Kim , Jong Seok Song , Sam Jin Her , Jun Heyoung Park
IPC: B32B15/00
CPC classification number: H05K3/381 , H05K1/0346 , H05K3/108 , H05K3/146 , H05K3/426 , H05K3/4644 , H05K2201/0154 , H05K2201/0959 , H05K2201/096 , H05K2203/092 , Y10S428/901 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24917
Abstract: Disclosed herein are a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The printed circuit board includes an insulating material; a via-hole formed in a given location of the insulating material; a copper seed layer formed through ion beam surface treatment and vacuum deposition on the surface of the insulating material having the via-hole formed therein; and a copper pattern plating layer formed on a given region of the insulating material, which has the copper seed layer formed thereon, and in the via-hole.
Abstract translation: 这里公开了一种印刷电路板及其制造方法,其可以通过实现超薄精细电路图案来改善电性能,缩短处理时间并减小芯片封装的厚度。 印刷电路板包括绝缘材料; 形成在绝缘材料的给定位置的通孔; 通过离子束表面处理形成的铜籽晶层,并且在其中形成有通孔的绝缘材料的表面上真空沉积; 以及形成在其上形成有铜种子层的绝缘材料的给定区域上的铜图案镀层和通孔。
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公开(公告)号:US20070261234A1
公开(公告)日:2007-11-15
申请号:US11709215
申请日:2007-02-22
Applicant: Jong Seok Song , Taehoon Kim , Dong Sun Kim , Hye Yeon Cha
Inventor: Jong Seok Song , Taehoon Kim , Dong Sun Kim , Hye Yeon Cha
CPC classification number: H05K3/381 , H05K3/108 , H05K3/146 , H05K3/4069 , H05K3/426 , H05K3/4602 , H05K2201/0959 , H05K2203/092 , H05K2203/1152 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
Abstract: Disclosed is a method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.
Abstract translation: 公开了一种积层印刷电路板的制造方法,其中通过使用干法形成芯层的金属种子层来实现包括芯层和外层的积层印刷电路板的电路 ,由离子束表面处理和真空沉积组成,代替常规的湿法,包括湿表面粗糙化处理和无电镀。 当在本发明的方法中用干法代替湿法时,电路层可以以环境友好的方式形成,并且可以制造包括芯层和外层的基片的所有电路层 通过半加成过程。 此外,可以提高树脂基板和金属层之间的剥离强度,从而实现高可靠性的精细电路。
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3.
公开(公告)号:US20070141310A1
公开(公告)日:2007-06-21
申请号:US11585276
申请日:2006-10-24
Applicant: Jong Seok Song , Taehoon Kim
Inventor: Jong Seok Song , Taehoon Kim
CPC classification number: H05K1/036 , B32B3/266 , B32B27/08 , B32B27/16 , B32B27/28 , B32B27/281 , B32B27/304 , B32B27/322 , B32B27/38 , B32B2255/10 , B32B2255/205 , B32B2255/26 , B32B2255/28 , B32B2307/728 , B32B2457/08 , C08J7/045 , H05K1/034 , H05K3/108 , H05K3/381 , H05K3/426 , H05K2201/015 , H05K2203/092 , Y10T428/24917
Abstract: Disclosed are a printed circuit board and a method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. According to this invention, the interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.
Abstract translation: 公开了一种印刷电路板及其制造方法,其中在树脂基板上形成氟树脂涂层,然后使用包括离子束表面处理和真空沉积的干法形成铜层,而不是形成铜层 常规湿法包括表面粗糙化和无电镀铜。 根据本发明,可以在不改变其表面粗糙度的情况下增加基板材料的界面粘合性,从而实现高可靠性的精细电路。 同样,由于氟树脂层的形成,可以获得低介电常数和低损耗系数。 此外,用干法代替湿法,由此可以以环境友好的方式形成铜镀层。
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公开(公告)号:US08065798B2
公开(公告)日:2011-11-29
申请号:US12805293
申请日:2010-07-22
Applicant: Dong Sun Kim , Taehoon Kim , Jong Seok Song , Sam Jin Her , Jun Heyoung Park
Inventor: Dong Sun Kim , Taehoon Kim , Jong Seok Song , Sam Jin Her , Jun Heyoung Park
CPC classification number: H05K3/381 , H05K1/0346 , H05K3/108 , H05K3/146 , H05K3/426 , H05K3/4644 , H05K2201/0154 , H05K2201/0959 , H05K2201/096 , H05K2203/092 , Y10S428/901 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24917
Abstract: A fabrication method which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The method for fabricating a printed circuit board includes: providing an insulating material; forming in the insulating material at least one via-hole for interlayer electrical connection; ion beam treating the surface of the insulating material having the via-hole formed therein; forming a copper seed layer on the surface-treated insulating material using a vacuum deposition process; and plating a copper pattern on the copper seed layer to form a circuit pattern.
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公开(公告)号:US07707716B2
公开(公告)日:2010-05-04
申请号:US11709215
申请日:2007-02-22
Applicant: Jong Seok Song , Taehoon Kim , Dong Sun Kim , Hye Yeon Cha
Inventor: Jong Seok Song , Taehoon Kim , Dong Sun Kim , Hye Yeon Cha
IPC: H01K3/10
CPC classification number: H05K3/381 , H05K3/108 , H05K3/146 , H05K3/4069 , H05K3/426 , H05K3/4602 , H05K2201/0959 , H05K2203/092 , H05K2203/1152 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
Abstract: A method of manufacturing a build-up printed circuit board, in which the circuit of a build-up printed circuit board including a core layer and an outer layer is realized by forming the metal seed layer of the core layer using a dry process, consisting of ion beam surface treatment and vacuum deposition, instead of a conventional wet process, including a wet surface roughening process and electroless plating. When the wet process is replaced with the dry process in the method of the invention, the circuit layer can be formed in an environmentally friendly manner, and as well, all circuit layers of the substrate including the core layer and the outer layer can be manufactured through a semi-additive process. Further, the peel strength between the resin substrate and the metal layer can be increased, thus realizing a highly reliable fine circuit.
Abstract translation: 一种积层印刷电路板的制造方法,其中通过使用干法形成芯层的金属种子层来实现包括芯层和外层的积层印刷电路板的电路,其包括 的离子束表面处理和真空沉积,而不是常规的湿法,包括湿表面粗糙化处理和无电镀。 当在本发明的方法中用干法代替湿法时,电路层可以以环境友好的方式形成,并且可以制造包括芯层和外层的基片的所有电路层 通过半加成过程。 此外,可以提高树脂基板和金属层之间的剥离强度,从而实现高可靠性的精细电路。
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公开(公告)号:US20110099807A1
公开(公告)日:2011-05-05
申请号:US12805293
申请日:2010-07-22
Applicant: Dong Sun Kim , Taehoon Kim , Jong Seok Song , Sam Jin Her , Jun Heyoung Park
Inventor: Dong Sun Kim , Taehoon Kim , Jong Seok Song , Sam Jin Her , Jun Heyoung Park
CPC classification number: H05K3/381 , H05K1/0346 , H05K3/108 , H05K3/146 , H05K3/426 , H05K3/4644 , H05K2201/0154 , H05K2201/0959 , H05K2201/096 , H05K2203/092 , Y10S428/901 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/24917
Abstract: A fabrication method which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The method for fabricating a printed circuit board includes: providing an insulating material; forming in the insulating material at least one via-hole for interlayer electrical connection; ion beam treating the surface of the insulating material having the via-hole formed therein; forming a copper seed layer on the surface-treated insulating material using a vacuum deposition process; and plating a copper pattern on the copper seed layer to form a circuit pattern.
Abstract translation: 通过实现超薄精细电路图案,能够提高电性能,缩短加工时间,减小芯片封装的厚度的制造方法。 制造印刷电路板的方法包括:提供绝缘材料; 在所述绝缘材料中形成至少一个用于层间电连接的通孔; 离子束处理其中形成有通孔的绝缘材料的表面; 使用真空沉积工艺在表面处理的绝缘材料上形成铜种子层; 并在铜籽晶层上镀铜图案以形成电路图案。
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公开(公告)号:US20100021649A1
公开(公告)日:2010-01-28
申请号:US12461960
申请日:2009-08-28
Applicant: Jong Seok Song , Taehoon Kim
Inventor: Jong Seok Song , Taehoon Kim
CPC classification number: H05K1/036 , B32B3/266 , B32B27/08 , B32B27/16 , B32B27/28 , B32B27/281 , B32B27/304 , B32B27/322 , B32B27/38 , B32B2255/10 , B32B2255/205 , B32B2255/26 , B32B2255/28 , B32B2307/728 , B32B2457/08 , C08J7/045 , H05K1/034 , H05K3/108 , H05K3/381 , H05K3/426 , H05K2201/015 , H05K2203/092 , Y10T428/24917
Abstract: A method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. The interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.
Abstract translation: 其制造方法是在树脂基板上形成氟树脂涂层,然后使用包括离子束表面处理和真空沉积的干法形成铜层,而不是常规的包括表面粗糙化的湿法, 化学镀铜。 可以增加基板材料的界面粘附性而不改变其表面粗糙度,从而实现高可靠性的精细电路。 同样,由于氟树脂层的形成,可以获得低介电常数和低损耗系数。 此外,用干法代替湿法,由此可以以环境友好的方式形成铜镀层。
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8.
公开(公告)号:US07601419B2
公开(公告)日:2009-10-13
申请号:US11585276
申请日:2006-10-24
Applicant: Jong Seok Song , Taehoon Kim
Inventor: Jong Seok Song , Taehoon Kim
IPC: B32B15/00
CPC classification number: H05K1/036 , B32B3/266 , B32B27/08 , B32B27/16 , B32B27/28 , B32B27/281 , B32B27/304 , B32B27/322 , B32B27/38 , B32B2255/10 , B32B2255/205 , B32B2255/26 , B32B2255/28 , B32B2307/728 , B32B2457/08 , C08J7/045 , H05K1/034 , H05K3/108 , H05K3/381 , H05K3/426 , H05K2201/015 , H05K2203/092 , Y10T428/24917
Abstract: Disclosed are a printed circuit board and a method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. According to this invention, the interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.
Abstract translation: 公开了一种印刷电路板及其制造方法,其中在树脂基板上形成氟树脂涂层,然后使用包括离子束表面处理和真空沉积的干法形成铜层,而不是形成铜层 常规湿法包括表面粗糙化和无电镀铜。 根据本发明,可以在不改变其表面粗糙度的情况下增加基板材料的界面粘合性,从而实现高可靠性的精细电路。 同样,由于形成氟树脂层,可以获得低介电常数和低损耗系数。 此外,用干法代替湿法,由此可以以环境友好的方式形成铜镀层。
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公开(公告)号:USD731382S1
公开(公告)日:2015-06-09
申请号:US29473154
申请日:2013-11-19
Applicant: Dinesh Mana , Taehoon Kim
Designer: Dinesh Mana , Taehoon Kim
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公开(公告)号:US08970046B2
公开(公告)日:2015-03-03
申请号:US13546163
申请日:2012-07-11
Applicant: Young Lyong Kim , Taehoon Kim , Jongho Lee , Chul-Yong Jang
Inventor: Young Lyong Kim , Taehoon Kim , Jongho Lee , Chul-Yong Jang
IPC: H01L25/07 , H01L23/31 , H01L23/00 , H01L25/065 , H01L25/00
CPC classification number: H01L21/76802 , H01L23/3121 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/92144 , H01L2225/06524 , H01L2225/06562 , H01L2225/06568 , H01L2924/01012 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/00
Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.
Abstract translation: 半导体封装可以包括:衬底,其包括衬底连接端子,堆叠在衬底上并具有芯片连接端子的至少一个半导体芯片,覆盖衬底和至少一个半导体芯片的至少一部分的第一绝缘层和/ 或穿透第一绝缘层的互连以将衬底连接端子连接到芯片连接端子。 半导体封装可以包括堆叠的半导体芯片,半导体芯片的边缘部分构成阶梯结构,并且每个半导体芯片包括芯片连接端子; 至少一个绝缘层,至少覆盖半导体芯片的边缘部分; 和/或穿透至少一个绝缘层的互连以连接到每个半导体芯片的芯片连接端子。
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