公开(公告)号：US5759873A

公开(公告)日：1998-06-02

申请号：US733207

申请日：1996-10-17

申请人： Keiichiro Kata ,  Shuichi Matsuda ,  Hironori Ono

发明人： Keiichiro Kata ,  Shuichi Matsuda ,  Hironori Ono

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/544 ,  H01L21/44 ,  H01L21/50

CPC分类号： H01L24/86 ,  H01L21/4803 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/41

摘要： In a method of manufacturing a chip size semiconductor device comprising a semiconductor chip and a carrier tape including an insulating film and wiring patterns formed on one surface of the insulating film, the method comprises the steps of bonding the semiconductor chip and the carrier tape by the use of an adhesive film having a predetermined size corresponding to an adhesive area of the semiconductor chip. The step of bonding comprises the substeps of cutting away the adhesive film by punching from an adhesive film tape held above the semiconductor chip mounted on a table and subsequently setting the adhesive film on the adhesive area by moving the adhesive film downwardly.

摘要翻译： 在制造包括半导体芯片的芯片尺寸半导体器件的方法和包括绝缘膜的载带和形成在绝缘膜的一个表面上的布线图案的方法中，所述方法包括以下步骤：将半导体芯片和载带 使用具有对应于半导体芯片的粘合区域的预定尺寸的粘合剂膜。 接合步骤包括通过从保持在安装在工作台上的半导体芯片上方的粘合薄膜带上冲下来切割粘合剂膜的子步骤，然后通过向下移动粘合剂膜将粘合剂膜设置在粘合剂区域上。

公开(公告)号：US5726489A

公开(公告)日：1998-03-10

申请号：US531271

申请日：1995-09-20

申请人： Shuichi Matsuda ,  Keiichiro Kata

发明人： Shuichi Matsuda ,  Keiichiro Kata

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/552 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/552 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15311

摘要： A film carrier semiconductor device 10 comprises a semiconductor bare chip 20 and a carrier film 30. Chip electrodes 21 are provided on the bare chip 20. Each chip electrode 21 is electrically connected to the carrier film 30. Bump electrodes 37 are formed and arranged as an array on the carrier film 30 on the side of the other surface 31b of the film 30. Interconnection layers 32 are provided on the carrier film 30 to connect some of the chip electrodes 21b to the bump electrodes 37a and 37b. The semiconductor device 10 also comprises a noise blocking layer 60 provided on the carrier film 30 outside the chip mounting region. The noise blocking layer 60 is electrically connected to at least one of the chip electrodes 21a.

摘要翻译： 膜载体半导体器件10包括半导体裸芯片20和载体膜30.芯片电极21设置在裸芯片20上。每个芯片电极21电连接到载体膜30.凸起电极37形成并布置为 在膜30的另一个表面31b侧的载体膜30上的阵列。在载体膜30上设置有互连层32，以将一些芯片电极21b连接到凸块电极37a和37b。 半导体器件10还包括设置在芯片安装区域外部的载体膜30上的噪声阻挡层60。 噪声阻挡层60电连接到芯片电极21a中的至少一个。

公开(公告)号：US5905303A

公开(公告)日：1999-05-18

申请号：US873593

申请日：1997-06-12

申请人： Keiichiro Kata ,  Shuichi Matsuda ,  Eiji Hagimoto

发明人： Keiichiro Kata ,  Shuichi Matsuda ,  Eiji Hagimoto

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L23/4985 ,  H01L23/3107 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  Y10T29/49121

摘要： An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.

摘要翻译： 绝缘膜在第一表面上具有导电层，在第二表面上具有导电突起。 导电层通过设置在绝缘膜中的通孔与导电突起连接。 具有焊盘的半导体芯片通过粘合剂层粘附到绝缘膜。 然后，导电层被局部加压，使得导电层电连接到相应的焊盘。

公开(公告)号：US5897337A

公开(公告)日：1999-04-27

申请号：US533205

申请日：1995-09-25

申请人： Keiichiro Kata ,  Shuichi Matsuda

发明人： Keiichiro Kata ,  Shuichi Matsuda

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495 ,  H01L21/283 ,  H01L21/58

CPC分类号： H01L21/563 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49572 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/83191 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311

摘要： In a method of manufacturing a semiconductor device comprising a semiconductor chip and a carrier film which includes an insulating film and wiring patterns formed on one of main surfaces of the insulating film, an adhesive layer is formed on a surface of a semiconductor wafer having a number of integrated circuits. Each of the integrated circuits has electrode pads for external connection on the foregoing surface of the semiconductor wafer. Subsequently, openings are formed at regions of the adhesive layer corresponding to the electrode pads, and then, the semiconductor wafer is cut per integrated circuit so as to obtain the semiconductor chips. Thereafter, the electrode pads of the semiconductor chip and the wiring patterns of the carrier film are connected to each other through the corresponding openings of the adhesive layer, respectively. Then, the semiconductor chip and the carrier film are bonded together via the adhesive layer interposed therebetween. It may be arranged that the adhesive layer is formed on the carrier film rather than on the semiconductor chip.

摘要翻译： 在制造包括半导体芯片和载体膜的半导体器件的方法中，其包括绝缘膜和形成在绝缘膜的一个主表面上的布线图案，在具有数字的半导体晶片的表面上形成粘合剂层 的集成电路。 每个集成电路在半导体晶片的上述表面上具有用于外部连接的电极焊盘。 随后，在与电极焊盘相对应的粘合剂层的区域处形成开口，然后每个集成电路切割半导体晶片，以获得半导体芯片。 此后，半导体芯片的电极焊盘和载体膜的布线图案分别通过粘合剂层的相应开口相互连接。 然后，半导体芯片和载体膜通过其间的粘合层粘合在一起。 可以设置粘合剂层形成在载体膜上，而不是形成在半导体芯片上。

公开(公告)号：US5683942A

公开(公告)日：1997-11-04

申请号：US450728

申请日：1995-05-25

申请人： Keiichiro Kata ,  Shuichi Matsuda ,  Eiji Hagimoto

发明人： Keiichiro Kata ,  Shuichi Matsuda ,  Eiji Hagimoto

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/4985 ,  H01L23/3107 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  Y10T29/49121

摘要： An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.

摘要翻译： 绝缘膜在第一表面上具有导电层，在第二表面上具有导电突起。 导电层通过设置在绝缘膜中的通孔与导电突起连接。 具有焊盘的半导体芯片通过粘合剂层粘附到绝缘膜。 然后，导电层被局部加压，使得导电层电连接到相应的焊盘。

公开(公告)号：US06339337B1

公开(公告)日：2002-01-15

申请号：US09048045

申请日：1998-03-26

申请人： Shuichi Matsuda ,  Keiichiro Kata ,  Ryoji Sato ,  Masaharu Sato

发明人： Shuichi Matsuda ,  Keiichiro Kata ,  Ryoji Sato ,  Masaharu Sato

IPC分类号： G01R3102

CPC分类号： G01R31/311

摘要： An infrared ray test for a semiconductor chip is conducted by irradiating infrared ray onto a bottom surface of a semiconductor chip, receiving the infrared ray reflected from a bonding pad and displaying the image of the bonding pad on a monitor. The image obtained from the infrared ray has information whether the bonding pad itself or a portion of the silicon substrate underlying the bonding pad has a defect or whether or not there is a deviation of the bonding pad with respect to the bump.

摘要翻译： 通过将红外线照射到半导体芯片的底面上，接收从接合焊盘反射的红外线并将接合焊盘的图像显示在监视器上，进行半导体芯片的红外线测试。 从红外线获得的图像具有关于焊盘本身或接合焊盘下方的硅衬底的一部分是否具有缺陷的焊盘的位置，或者接合焊盘相对于凸块是否存在偏差的信息。

公开(公告)号：US5757068A

公开(公告)日：1998-05-26

申请号：US533208

申请日：1995-09-25

申请人： Keiichiro Kata ,  Shuichi Matsuda

发明人： Keiichiro Kata ,  Shuichi Matsuda

IPC分类号： H01L21/60 ,  H01L23/495 ,  H01L23/48 ,  H05K7/20

CPC分类号： H01L23/49572 ,  H01L2224/16 ,  H01L2924/01079

摘要： There is provided a carrier film (130, 140) having a plurality of slits (135) formed by the periphery of a chip mounting region (138) on which a semiconductor chip 10 is to be mounted. The chip mounting region is rectangular and four slits are formed along the four sides of the chip mounting region. The slits may be formed by means of punching with a die or etching.

摘要翻译： 提供了一种载体膜（130,140），其具有由芯片安装区域（138）的周围形成的多个狭缝（135），半导体芯片10将要安装在该芯片安装区域周围。 芯片安装区域是矩形的，并且沿着芯片安装区域的四个边缘形成四个狭缝。 狭缝可以通过用模具冲压或蚀刻来形成。

公开(公告)号：US06794750B2

公开(公告)日：2004-09-21

申请号：US09222524

申请日：1998-12-28

申请人： Shuichi Matsuda

发明人： Shuichi Matsuda

IPC分类号： H01L2343

CPC分类号： H01L23/4985 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor device equipped with a TAB (tape automated bonding) tape. A desired pattern of wiring is formed on one surface of the TAB tape and a semiconductor chip having two or more chip electrodes is disposed on the other surface of the TAB tape. The wiring and the chip electrodes are electrically interconnected via bumps that are formed in through-holes of the wiring in conforming relationship with the chip electrodes. This prevents fault connection between the chip electrodes and the bumps.

摘要翻译： 一种配有TAB（胶带自动贴合）胶带的半导体器件。 在TAB带的一个表面上形成所需的布线图案，并且在TAB带的另一个表面上设置具有两个或更多个芯片电极的半导体芯片。 布线和芯片电极通过与芯片电极成一致的关系形成在布线的通孔中的凸块电连接。 这防止了芯片电极和凸块之间的故障连接。

公开(公告)号：US4792461A

公开(公告)日：1988-12-20

申请号：US64392

申请日：1987-06-22

申请人： Yaichiro Watakabe ,  Shuichi Matsuda

发明人： Yaichiro Watakabe ,  Shuichi Matsuda

IPC分类号： G03F1/00 ,  G03F1/54 ,  H01L21/027 ,  B05D3/06

CPC分类号： G03F1/54 ,  Y10S148/019 ,  Y10S148/147 ,  Y10T428/2395

摘要： A silicide film of oxidized transition metal 3 formed on a transparent substrate 1 has a low reflectance and in consequence, a high resolution can be obtained and dry etching thereof can be easily done. In addition, since said silicide film 3 has good adhesion to a transparent substrate 1, file patterns therein do not peel off at the time of rinsing the mask.

摘要翻译： 形成在透明基板1上的氧化过渡金属3的硅化物膜具有低反射率，因此可以获得高分辨率，并且可以容易地进行干蚀刻。 此外，由于所述硅化物膜3对透明基板1具有良好的粘附性，因此在清洗掩模时，其中的文件图案不会剥落。

公开(公告)号：US5757078A

公开(公告)日：1998-05-26

申请号：US637281

申请日：1996-04-24

申请人： Shuichi Matsuda ,  Kazutaka Shoji

发明人： Shuichi Matsuda ,  Kazutaka Shoji

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/485 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

摘要： A semiconductor device including a semiconductor chip having electrode pads, a package composed of a plurality of insulating films and adhered to the semiconductor chip by an adhesive agent. The package includes wiring patterns interposed between the plurality of insulating films, and the wiring patterns are selectively connected to the electrode pads at one end, and to the plurality of electrically conductive protrusions at the other end, via viaholes. The semiconductor device further includes a plurality of electrically conductive protrusions extending from the outermost wiring patterns via the viaholes provided in the outermost insulating film.

摘要翻译： 一种半导体器件，包括具有电极焊盘的半导体芯片，由多个绝缘膜构成的封装，并通过粘合剂粘附到半导体芯片。 封装包括插入在多个绝缘膜之间的布线图案，并且布线图案在一端被选择性地连接到电极焊盘，并且在另一端通过通孔选择性地连接到多个导电突起。 半导体器件还包括从最外面的布线图形经由设置在最外层绝缘膜中的通孔延伸的多个导电突起。