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19 条记录 (耗时 0.018 秒)

    Voltage regulation for semiconductor dies and related structure
    1.
    发明授权
    Voltage regulation for semiconductor dies and related structure 有权
    半导体管芯电压调节及相关结构

    公开(公告)号：US06674646B1

    公开(公告)日：2004-01-06

    申请号：US09971162

    申请日：2001-10-05

    申请人： Khosrow Golshan ,  Siamak Fazelpour ,  Hassan S. Hashemi

    发明人： Khosrow Golshan ,  Siamak Fazelpour ,  Hassan S. Hashemi

    IPC分类号： H05K702

    CPC分类号： H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

    摘要翻译： 电压调节器的输出是与包装衬底上的管芯附着区相邻的核心电压线。 电压调节器的输入通常耦合到电源，在一个实施例中，电源也是与芯片附接区域相邻的I / O电压线。 在一个实施例中，芯电压线被成形为环绕包装衬底上的管芯附着区域的环。 在另一个实施例中，I / O电压线也被成形为环绕包装衬底上的管芯附着区域的环。 此外，具有至少一个I / O Vdd接合焊盘和至少一个芯Vdd接合焊盘的半导体管芯可以安装在管芯附着区域中。 I / O Vdd接合焊盘和内核Vdd接合焊盘可以分别连接到I / O电压环和核心电压环。

    Controlled impedance transmission lines in a redistribution layer
    3.
    发明授权
    Controlled impedance transmission lines in a redistribution layer 有权
    再分配层中的受控阻抗传输线

    公开(公告)号：US06674174B2

    公开(公告)日：2004-01-06

    申请号：US10012812

    申请日：2001-11-13

    申请人： Surasit Chungpaiboonpatana ,  Hassan S. Hashemi ,  Siamak Fazelpour

    发明人： Surasit Chungpaiboonpatana ,  Hassan S. Hashemi ,  Siamak Fazelpour

    IPC分类号： H01L2348

    CPC分类号： H01L23/647 ,  H01L23/3114 ,  H01L23/525 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/3011

    摘要： In one embodiment, the invention includes first and second transmission lines fabricated in a redistribution layer over a semiconductor die. The first transmission line has a first distance from a first ground return path formed in a first metal level. The first transmission line has a first impedance corresponding to the first distance. In other words, the impedance of the first transmission line is affected by the distance between the first transmission line and the first ground return path. Similar to the first transmission line, the second transmission line has a second distance from a second ground return path formed in a second metal level. The second transmission line has a second impedance corresponding to the second distance. In other words, the impedance of the second transmission line is affected by the distance between the second transmission line and the second ground return path.

    摘要翻译： 在一个实施例中，本发明包括在半导体管芯上的再分配层中制造的第一和第二传输线。 第一传输线具有与形成在第一金属层中的第一接地返回路径的第一距离。 第一传输线具有对应于第一距离的第一阻抗。 换句话说，第一传输线的阻抗受到第一传输线和第一接地返回路径之间的距离的影响。 与第一传输线类似，第二传输线具有形成在第二金属级的第二接地返回路径的第二距离。 第二传输线具有对应于第二距离的第二阻抗。 换句话说，第二传输线的阻抗受到第二传输线和第二接地返回路径之间的距离的影响。

    Pin grid array package with controlled impedance pins
    4.
    发明授权
    Pin grid array package with controlled impedance pins 有权
    具有受控阻抗引脚的引脚格栅阵列封装

    公开(公告)号：US06534854B1

    公开(公告)日：2003-03-18

    申请号：US10005564

    申请日：2001-11-08

    申请人： Siamak Fazelpour ,  Hassan S. Hashemi ,  Roberto Coccioli

    发明人： Siamak Fazelpour ,  Hassan S. Hashemi ,  Roberto Coccioli

    IPC分类号： H01L2348

    CPC分类号： H01L23/49811 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/3011 ,  H05K1/0219 ,  H01L2924/00

    摘要： A pin grid array package comprises a number of signal pins and ground pins. At least one of the signal pins is a controlled impedance signal pin, i.e. a signal pin whose impedance is adjusted and/or reduced according to the present invention. The pin grid array package also includes a number of ground planes and signal planes. A controlled impedance signal pin is coupled to one of the signal planes by means of a signal via. A number of ground pins surround the controlled impedance signal pin. By varying the arrangement, number, and separation distance between the ground pins and the controlled impedance signal pin, the impedance of the signal pin is adjusted and/or reduced. Depending on the particular circuit or logic function assigned to a signal pin and its adjacent signal pin, a different degree of impedance control and/or reduction can be achieved by the present invention.

    摘要翻译： 引脚格栅阵列封装包括多个信号引脚和接地引脚。 信号引脚中的至少一个是受控阻抗信号引脚，即根据本发明的阻抗被调整和/或减小的信号引脚。 引脚格栅阵列封装还包括多个接地层和信号面。 受控阻抗信号引脚通过信号通孔耦合到一个信号平面。 一些接地引脚环绕受控阻抗信号引脚。 通过改变接地引脚和受控阻抗信号引脚之间的布置，数量和间隔距离，信号引脚的阻抗被调整和/或减小。 根据分配给信号引脚及其相邻信号引脚的特定电路或逻辑功能，本发明可以实现不同程度的阻抗控制和/或减小。

    Leadless chip carrier design and structure
    6.
    发明授权
    Leadless chip carrier design and structure 有权
    无引脚芯片载体的设计和结构

    公开(公告)号：US06921972B1

    公开(公告)日：2005-07-26

    申请号：US09713834

    申请日：2000-11-15

    申请人： Hassan S. Hashemi

    发明人： Hassan S. Hashemi

    IPC分类号： H01L23/367 ,  H01L23/64 ,  H01L23/10 ,  H01L23/34

    CPC分类号： H01L23/64 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48235 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/8547 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor device is provided in the form of a chip carrier (e.g., chip/IC scale carrier for RF applications) that includes an integrated circuit chip attached to a die attach pad. The device has an interconnect substrate having an upper surface and a lower surface, with a plurality of vias passing through the thickness of the interconnect substrate from the upper surface to the lower surface. The die attach pad is located on the upper surface of the interconnect substrate, and a heat spreader is located on the lower surface of the interconnect substrate. A first group of vias is positioned to intersect both the die attach pad and the heat spreader. A second group of vias is positioned away from the die attach pad and the heat spreader. The upper surface has a plurality of bond pads that are abutting the second group of vias and the lower surface has a plurality of lands that are also abutting the second group of vias.

    摘要翻译： 以芯片载体（例如，用于RF应用的芯片/ IC标尺载体）的形式提供半导体器件，其包括附接到管芯附接焊盘的集成电路芯片。 该器件具有具有上表面和下表面的互连衬底，多个通孔从上表面到下表面穿过互连衬底的厚度。 管芯附接垫位于互连基板的上表面上，散热器位于互连基板的下表面上。 第一组通孔定位成与管芯附接垫和散热器相交。 第二组通孔位于远离管芯附接垫和散热器的位置。 上表面具有与第二组通孔邻接的多个接合焊盘，并且下表面具有也邻接第二组通孔的多个焊盘。