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    Wafer Arrangement and Method for Manufacturing a Wafer Arrangement
    3.
    发明申请
    Wafer Arrangement and Method for Manufacturing a Wafer Arrangement 审中-公开
    晶片布置及晶圆制造方法

    公开(公告)号：US20090001366A1

    公开(公告)日：2009-01-01

    申请号：US11778555

    申请日：2007-07-16

    申请人： Stephan Dobritz ,  Stefan Ruckmich

    发明人： Stephan Dobritz ,  Stefan Ruckmich

    IPC分类号： H01L23/58 ,  G01R31/26 ,  H01L21/66

    CPC分类号： H01L22/32 ,  G01R31/2884

    摘要： A wafer arrangement in accordance with an embodiment of the invention includes a wafer having a plurality of dice, wherein at least some of the dice have a first connection, and at least one contact pad formed at the wafer edge, wherein a plurality of first connections are coupled by means of a section of a redistribution layer and the contact pad is formed by the section of the redistribution layer.

    摘要翻译： 根据本发明的实施例的晶片布置包括具有多个裸片的晶片，其中至少一些裸片具有第一连接，以及形成在晶片边缘处的至少一个接触焊盘，其中多个第一连接 通过再分配层的一部分耦合，并且接触垫由再分布层的部分形成。

    Arrangement for reducing the electrical crosstalk on a chip
    4.
    发明申请
    Arrangement for reducing the electrical crosstalk on a chip 审中-公开
    用于减少芯片上的电串扰的布置

    公开(公告)号：US20050275085A1

    公开(公告)日：2005-12-15

    申请号：US11140578

    申请日：2005-05-27

    申请人： Axel Brintzinger ,  Octavio Trovarelli ,  Ingo Uhlendorf ,  Stefan Ruckmich ,  David Wallis ,  Fritz Uhlendorf ,  Helga Uhlendorf

    发明人： Axel Brintzinger ,  Octavio Trovarelli ,  Ingo Uhlendorf ,  Stefan Ruckmich ,  David Wallis ,  Fritz Uhlendorf ,  Helga Uhlendorf

    IPC分类号： H01L23/12 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L23/5222 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor (10) being respectively arranged between adjacent conductors of the redistribution routing (1) and/or at least a second passivation (7) with a lower dielectric constant of a preferred “cold dielectric” being arranged between the redistribution routing (1) and the first passivation (2) on the active region of the chip (3).

    摘要翻译： 一种布置减少了芯片上的电串扰，特别是在再分配路由的相邻导体之间和/或芯片上的第一钝化上的再分配布线之间以及芯片的金属化之间的电串扰。 在一个方面，该布置减少了芯片上的再分配布线与其金属化之间的串扰，并且可以在前端简单且独立地实现。 这通过分别布置在再分配路由（1）的相邻导体和/或至少第二钝化层（7）之间的至少一个额外的导体（10）来实现，其中优选的“冷电介质”的较低介电常数被布置 在芯片（3）的有源区域上的再分配路由（1）和第一钝化（2）之间。

    Electronic component with compliant elevations having electrical contact areas and method for producing it
    5.
    发明授权
    Electronic component with compliant elevations having electrical contact areas and method for producing it 有权
    具有具有电接触区域的顺应性高度的电子部件及其制造方法

    公开(公告)号：US07368375B2

    公开(公告)日：2008-05-06

    申请号：US10997761

    申请日：2004-11-24

    申请人： Axel Brintzinger ,  Stefan Ruckmich ,  Octavio Trovarelli

    发明人： Axel Brintzinger ,  Stefan Ruckmich ,  Octavio Trovarelli

    IPC分类号： H01L21/31

    CPC分类号： H01L23/49811 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The compliant elevations are arranged on a surface of the component and the electrical contact areas are arranged on the tip of the compliant elevations. The electrical contact with the electronic circuit is embodied by means of electrical conductive tracks arranged on the surface of the component. The conductive tracks ascend on the outer surfaces of the compliant elevations to the electrical contact areas.

    摘要翻译： 电子部件包括具有用于将部件与电子电路接触连接的电接触区域的柔性凸起。 顺应性高度布置在部件的表面上，并且电接触区域布置在顺应性高度的尖端上。 与电子电路的电接触通过布置在部件的表面上的导电轨道来实现。 导电轨道在顺应性高度的外表面上升到电接触区域。

    Method for producing a rewiring printed circuit board
    6.
    发明申请
    Method for producing a rewiring printed circuit board 有权
    一种重新布线印刷电路板的制造方法

    公开(公告)号：US20060121257A1

    公开(公告)日：2006-06-08

    申请号：US11251594

    申请日：2005-10-14

    申请人： Axel Brintzinger ,  Stefan Ruckmich ,  Octavio Trovarelli ,  David Wallis

    发明人： Axel Brintzinger ,  Stefan Ruckmich ,  Octavio Trovarelli ,  David Wallis

    IPC分类号： C23C26/00 ,  B05D5/12 ,  B32B3/10 ,  B32B3/00

    CPC分类号： H01L23/49827 ,  H01L21/4846 ,  H01L21/486 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0306 ,  H05K2201/09609 ,  Y10S438/976 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00

    摘要： The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

    摘要翻译： 本发明涉及一种用于生产具有在第一和第二表面之间具有通道连接的基底晶片的再布线印刷电路板的方法。 该方法的一个实施例包括在第一和第二表面上施加和图案化掩模层，从而揭露第一表面上的第一接触位置和第二表面上的第二接触位置; 在第二表面施加保护层，以便在随后的方法步骤期间保护相应的掩蔽层和第二接触位置; 将第一导体结构施加到第一表面，第一表面上的第一导体结构覆盖第一接触位置; 去除第二表面上的保护层; 以及将第二导体结构施加到所述第二表面，所述第二表面上的所述第二导体结构覆盖所述第二接触位置。

    REDUCING DEFECTS IN ELECTRONIC APPARATUS
    8.
    发明申请
    REDUCING DEFECTS IN ELECTRONIC APPARATUS 审中-公开
    减少电子设备的缺陷

    公开(公告)号：US20130134126A1

    公开(公告)日：2013-05-30

    申请号：US13701788

    申请日：2011-06-03

    申请人： Dorota Kowal-Paul ,  Enrico Bellmann ,  Oisin Kenny ,  Stefan Ruckmich

    发明人： Dorota Kowal-Paul ,  Enrico Bellmann ,  Oisin Kenny ,  Stefan Ruckmich

    IPC分类号： H05K13/00

    CPC分类号： H05K13/00 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68386

    摘要： A technique, comprising defining at least part of one or more electronic devices on a substrate sheet by means of one or more material removal processes, wherein the substrate sheet is arranged on a lower layer so as to overhang said lower layer more at a first end than it does at an opposite, second end; and removing loose material from under said overhang at said first end by means of a stream of gas directed at said substrate and said lower layer from an outlet, said stream of gas having at said outlet at least a directional component parallel to a direction from said second end to said first end.

    摘要翻译： 一种技术，其包括通过一个或多个材料去除工艺在衬底片上限定一个或多个电子器件的至少一部分，其中所述衬底布置在下层上，以便在第一端更多地伸出所述下层 而不是在相反的第二端; 并且在所述第一端处通过从所述基底和所述下层排出的气流从所述出口除去在所述突出部下方的松散材料，所述气体流在所述出口处具有至少一个平行于所述第一端的方向的方向分量 第二端到所述第一端。