公开(公告)号：US07061347B2

公开(公告)日：2006-06-13

申请号：US10749917

申请日：2003-12-31

Applicant: Kun-Ching Chen ,  Sung-Mao Wu

Inventor： Kun-Ching Chen ,  Sung-Mao Wu

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H01P3/088 ,  H05K1/024 ,  H05K3/4688 ,  H05K2201/015 ,  H05K2201/0187 ,  H05K2201/09309

Abstract: A high frequency substrate includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a high-frequency signal transmission line. The first dielectric layer is formed on the first metal layer, and the second metal layer is formed on the first dielectric layer. The first and second metal layers are maintained in a stable voltage status due to the high dielectric coefficient of the first dielectric layer. Besides, the second dielectric layer is formed on the second metal layer. High speed and high frequency transmission are achieved when signals transmitting in the high-frequency transmission line formed on the second dielectric layer due to the low dielectric coefficient of the second dielectric layer.

Abstract translation: 高频基板包括第一金属层，第一介电层，第二金属层，第二介电层和高频信号传输线。 第一介电层形成在第一金属层上，第二金属层形成在第一介电层上。 由于第一介电层的高介电系数，第一和第二金属层保持在稳定的电压状态。 此外，第二介电层形成在第二金属层上。 由于第二电介质层的低介电系数，在形成在第二电介质层上的高频传输线中的信号传输时，实现了高速和高频传输。

公开(公告)号：US07061084B2

公开(公告)日：2006-06-13

申请号：US10655296

申请日：2003-09-05

Applicant: Kun-Ching Chen ,  Yung I Yeh

Inventor： Kun-Ching Chen ,  Yung I Yeh

IPC: H01L23/06

CPC classification number: H01L21/4857 ,  H01L23/13 ,  H01L23/3114 ,  H01L24/50 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K3/4092 ,  H05K3/4652 ,  H01L2924/00

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections. This invention also provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package

公开(公告)号：US06680529B2

公开(公告)日：2004-01-20

申请号：US10075227

申请日：2002-02-15

Applicant: Kun-Ching Chen ,  Yi-Chuan Ding ,  In-De Ou

Inventor： Kun-Ching Chen ,  Yi-Chuan Ding ,  In-De Ou

IPC: H01L2334

CPC classification number: H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract translation: 半导体积层封装包括管芯，电路板和至少介电层。 电路板具有用于构建电介质层的表面，并且该表面具有用于容纳模具的空腔。 多层电路板的内部具有扩展半导体集成封装的电气功能的导电迹线。 每个电介质层具有导电柱，使得管芯可以与最外层电介质层电连接。 至少导电柱结合在多层电路板的表面上用于内部电连接。

公开(公告)号：US06750397B2

公开(公告)日：2004-06-15

申请号：US10075226

申请日：2002-02-15

Applicant: In-De Ou ,  Yi-Chuan Ding ,  Kun-Ching Chen

Inventor： In-De Ou ,  Yi-Chuan Ding ,  Kun-Ching Chen

IPC: H01L2302

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L24/19 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541

Abstract: A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Abstract translation: 半导体积层封装包括管芯，金属载体和多个电介质层。 金属载体具有用于支撑模具的空腔的表面。 金属载体的表面与用于建立多个电介质层的管芯的有源表面共面。 每个电介质层具有用于内部电连接的金属柱。 金属载体覆盖模具的被动表面和侧面，具有较大的散热面积，因此从模具产生的热量通过金属载体快速消散。

公开(公告)号：US06737300B2

公开(公告)日：2004-05-18

申请号：US10151042

申请日：2002-05-21

Applicant: Yi-Chuan Ding ,  Xin Hui Lee ,  Kun-Ching Chen

Inventor： Yi-Chuan Ding ,  Xin Hui Lee ,  Kun-Ching Chen

IPC: H01L2148

CPC classification number: H01L21/568 ,  H01L21/563 ,  H01L24/27 ,  H01L24/29 ,  H01L24/31 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/83951 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49171 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05599

Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Abstract translation: 芯片级封装主要包括通过各向异性导电粘合膜（ACF）附着到半导体芯片的有源表面的衬底。 衬底在其下表面上设置有多个接触焊盘，并且在其上表面上设置有多个焊盘，其中接触焊盘电耦合到相应的焊盘。 设置在基板的接触焊盘上的多个金属凸块。 基板上的金属凸块通过ACF电耦合到芯片上的对应焊盘。 衬底和ACF的侧面部分被密封在封装主体中。 本发明还提供了一种使芯片级封装在晶片级的方法。 该方法的特征在于一个接一个地将衬底附着到晶片的芯片上，以便大大减少与晶片和衬底之间的CTE失配相关的问题，从而显着提高了产品的产量。

公开(公告)号：US06423622B1

公开(公告)日：2002-07-23

申请号：US09514645

申请日：2000-02-29

Applicant: Kun-Ching Chen ,  Yung I Yeh

Inventor： Kun-Ching Chen ,  Yung I Yeh

IPC: H01L2144

CPC classification number: H01L24/84 ,  H01L21/4857 ,  H01L23/13 ,  H01L2224/37155 ,  H01L2224/3754 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K3/4092 ,  H05K3/4652 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections. This invention also provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package

Abstract translation: 引线键合型芯片封装包括用于支撑和互连半导体芯片的多层基板。 多层基板具有限定在其中的槽。 多层基板包括具有设置在其上的预浸料的层间电路板，层间电路板的上表面上的预浸料上的多个引线，以及用于在预浸料的下表面上进行外部电连接的多个焊盘 夹层电路板。 多层基板的引线被接合到形成在半导体芯片上的相应的接合焊盘。 在半导体芯片周围的多层基板和多层基板的槽中形成封装体。 多层基板能够提供形成在其中的电源或接地平面，以增强封装的电气性能，并提供高的布线密度以封装具有高I / O连接的芯片。 本发明还提供一种制造用于形成引线键合型芯片封装的多层基板的方法

公开(公告)号：US20100071937A1

公开(公告)日：2010-03-25

申请号：US12535895

申请日：2009-08-05

Applicant: Shih-Chang Lee ,  Kun-Ching Chen ,  Ming-Loung Lu ,  Chun-Che Lee

Inventor： Shih-Chang Lee ,  Kun-Ching Chen ,  Ming-Loung Lu ,  Chun-Che Lee

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/111 ,  H01L2224/48463 ,  H05K3/061 ,  H05K3/243 ,  H05K3/328 ,  H05K2201/09472 ,  H05K2201/09736 ,  H05K2203/0361 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: A circuit board includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region.

Abstract translation: 电路板包括电介质层，电路层和绝缘层。 电路层设置在电介质层上并具有焊盘区域和迹线区域。 绝缘层设置在电路层上并覆盖迹线区域。 这里，焊盘区域的厚度小于迹线区域的厚度。

公开(公告)号：US06642612B2

公开(公告)日：2003-11-04

申请号：US10195375

申请日：2002-07-16

Applicant: Kun-Ching Chen ,  Yung I Yeh

Inventor： Kun-Ching Chen ,  Yung I Yeh

IPC: H01L2306

CPC classification number: H01L24/84 ,  H01L21/4857 ,  H01L23/13 ,  H01L2224/37155 ,  H01L2224/3754 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K3/4092 ,  H05K3/4652 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections. This invention also provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package.

Abstract translation: 引线键合型芯片封装包括用于支撑和互连半导体芯片的多层基板。 多层基板具有限定在其中的槽。 多层基板包括具有设置在其上的预浸料的层间电路板，层间电路板的上表面上的预浸料上的多个引线，以及用于在预浸料的下表面上进行外部电连接的多个焊盘 夹层电路板。 多层基板的引线被接合到形成在半导体芯片上的相应的接合焊盘。 在半导体芯片周围的多层基板和多层基板的槽中形成封装体。 多层基板能够提供形成在其中的电源或接地平面，以增强封装的电气性能，并提供高的布线密度以封装具有高I / O连接的芯片。 本发明还提供一种制造用于形成引线键合型芯片封装的多层基板的方法。

公开(公告)号：US06528882B2

公开(公告)日：2003-03-04

申请号：US09849137

申请日：2001-05-04

Applicant: Yi-Chuan Ding ,  Chang-Chi Lee ,  Kun-Ching Chen ,  Yung-I Yeh

Inventor： Yi-Chuan Ding ,  Chang-Chi Lee ,  Kun-Ching Chen ,  Yung-I Yeh

IPC: H01L2334

CPC classification number: H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

公开(公告)号：US06191360B1

公开(公告)日：2001-02-20

申请号：US09298849

申请日：1999-04-26

Applicant: Su Tao ,  Han-Hsiang Huang ,  Kun-Ching Chen ,  Chun-Chi Lee

Inventor： Su Tao ,  Han-Hsiang Huang ,  Kun-Ching Chen ,  Chun-Chi Lee

IPC: H01L2302

CPC classification number: H01L23/585 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A BGA package includes a substrate, a chip, and a heat spreader. The spreader covers the chip, a bottom part of the spreader is mounted on an upper surface of the substrate by an adhesive. The spreader shields Electro Magnetic Interference to the chip. In addition, the substrate is made of a built-up PCB.

Abstract translation: BGA封装包括基板，芯片和散热器。 撒布机覆盖芯片，扩散器的底部通过粘合剂安装在基板的上表面上。 吊具屏蔽电磁干扰芯片。 此外，衬底由积累的PCB制成。