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1.发明授权Treatment for a microelectronic device and method of resisting damage to a microelectronic device using same 有权微电子器件的处理以及使用该微电子器件对微电子器件的损伤的方法公开(公告)号：US08304065B2
公开(公告)日：2012-11-06
申请号：US12655282
申请日：2009-12-28
申请人： Leonel Arana , Dingying Xu , Vijay Wakharkar , Wen Feng , Nirupama Chakrapani , Shankar Ganapathysubramanian , Jorge Sanchez , Mohit Mamodia
发明人： Leonel Arana , Dingying Xu , Vijay Wakharkar , Wen Feng , Nirupama Chakrapani , Shankar Ganapathysubramanian , Jorge Sanchez , Mohit Mamodia
IPC分类号： B32B7/02
CPC分类号： H01L21/6836 , H01L23/3164 , H01L24/81 , H01L2221/68327 , H01L2221/68377 , H01L2224/131 , H01L2224/16 , H01L2224/81007 , H01L2224/81815 , H01L2924/0001 , H01L2924/10253 , Y10T428/24124 , Y10T428/2419 , Y10T428/24942 , Y10T428/2495 , Y10T428/25 , Y10T428/2839 , Y10T428/2852 , Y10T428/31703 , H01L2924/014 , H01L2224/13099 , H01L2924/00
摘要： A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.
摘要翻译： 微电子器件的处理包括切割带（110）和添加有颜料或其它着色剂的聚合物复合膜（120），并且在一些实施方案中，预固化玻璃化转变温度大于50℃。 膜可以包括多层，一层是粘性的，另一层在给定温度下是非粘性的。
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2.发明申请Treatment for a microelectronic device and method of resisting damage to a microelectronic device using same 有权微电子器件的处理以及使用该微电子器件对微电子器件的损伤的方法公开(公告)号：US20110159256A1
公开(公告)日：2011-06-30
申请号：US12655282
申请日：2009-12-28
申请人： Leonel Arana , Dingying Xu , Vijay Wakharkar , Wen Feng , Nirupama Chakrapani , Shankar Ganapathysubramanian , Jorge Sanchez , Mohit Mamodia
发明人： Leonel Arana , Dingying Xu , Vijay Wakharkar , Wen Feng , Nirupama Chakrapani , Shankar Ganapathysubramanian , Jorge Sanchez , Mohit Mamodia
CPC分类号： H01L21/6836 , H01L23/3164 , H01L24/81 , H01L2221/68327 , H01L2221/68377 , H01L2224/131 , H01L2224/16 , H01L2224/81007 , H01L2224/81815 , H01L2924/0001 , H01L2924/10253 , Y10T428/24124 , Y10T428/2419 , Y10T428/24942 , Y10T428/2495 , Y10T428/25 , Y10T428/2839 , Y10T428/2852 , Y10T428/31703 , H01L2924/014 , H01L2224/13099 , H01L2924/00
摘要： A treatment for a microelectronic device comprises a dicing tape (110) and a polymer composite film (120) having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50° Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.
摘要翻译： 微电子器件的处理包括切割带（110）和添加有颜料或其它着色剂的聚合物复合膜（120），并且在一些实施方案中，预固化玻璃化转变温度大于50℃。 膜可以包括多层，一层是粘性的，另一层在给定温度下是非粘性的。
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公开(公告)号：US07759780B2
公开(公告)日：2010-07-20
申请号：US12242398
申请日：2008-09-30
申请人： Nirupama Chakrapani , Vijay S Wakharkar , Janet Feng , Nisha Ananthakrishnan , Shankar Ganapathysubramanian , Gregory S Constable
发明人： Nirupama Chakrapani , Vijay S Wakharkar , Janet Feng , Nisha Ananthakrishnan , Shankar Ganapathysubramanian , Gregory S Constable
IPC分类号： H01L23/29
CPC分类号： H01L23/373 , H01L23/3731 , H01L23/3732 , H01L23/3736 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/00 , H01L2224/0401
摘要： A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.
摘要翻译： 提供微电子封装。 微电子封装包括半导体衬底和具有顶表面和底表面的管芯，其中管芯的底表面耦合到半导体衬底。 微电子封装还包括设置在管芯的顶表面上的纳米材料层。
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公开(公告)号：US09123732B2
公开(公告)日：2015-09-01
申请号：US13631612
申请日：2012-09-28
申请人： Sandeep B. Sane , Shankar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
发明人： Sandeep B. Sane , Shankar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
CPC分类号： H01L24/32 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/89 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/3213 , H01L2224/32225 , H01L2224/32501 , H01L2224/32505 , H01L2224/73253 , H01L2224/81007 , H01L2224/81193 , H01L2224/81815 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/161 , H01L2924/16251 , H01L2924/3511 , H01L2924/00 , H01L2924/014
摘要： Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
摘要翻译： 控制模具翘曲，用于组装薄模具。 在一个示例中，形成具有背面上的基板和在前侧层中的部件的装置。 背衬层形成在衬底上，该层在加热器件时抵抗器件翘曲。 该装置通过加热连接到基板。
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公开(公告)号：US20120152601A1
公开(公告)日：2012-06-21
申请号：US13374858
申请日：2012-01-19
CPC分类号： H05K1/0201 , H01L21/4807 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/06 , H05K3/107 , H05K3/205 , H05K3/388 , H05K3/4617 , H05K3/4629 , H05K3/4647 , H05K2201/0175 , H05K2201/0187 , H05K2201/0376 , H05K2201/096 , H05K2201/09881 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
摘要翻译： 描述了用于封装衬底和管芯间隔件的层或层。 层或层包括位于平面内并由金属通孔分开的多个陶瓷阱。 陶瓷井内的凹陷由介电填料材料占据。
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6.发明授权Compliant structure for an electronic device, method of manufacturing same, and system containing same 有权用于电子设备的符合标准的结构，其制造方法和包含该装置的系统公开(公告)号：US07692307B2
公开(公告)日：2010-04-06
申请号：US11636250
申请日：2006-12-08
申请人： Sudarshan Rangaraj , Shankar Ganapathysubramanian , Richard Harries , Mitul Modi , Sankara J. Subramanian
发明人： Sudarshan Rangaraj , Shankar Ganapathysubramanian , Richard Harries , Mitul Modi , Sankara J. Subramanian
IPC分类号： H01L23/48
CPC分类号： H05K1/0271 , H01L23/13 , H01L2924/0002 , H05K3/3436 , H05K2201/0133 , H05K2201/0187 , H05K2201/068 , Y10T29/49158 , H01L2924/00
摘要： A compliant structure for an electronic device comprises a substrate (110) composed of a first material (111) and a compliant zone (120) within the substrate. A plurality of solder joints (280) are located between, and form a connection between, the substrate and the electronic device (290). The compliant zone reduces the degree of deformation experienced by the solder joints due to thermal mismatch loading between the substrate and the die during attachment of the die to the substrate (chip attach). This reduction in solder joint deformation reduces the likelihood that the solder joints will crack.
摘要翻译： 用于电子设备的柔性结构包括由衬底内的第一材料（111）和柔性区（120）组成的衬底（110）。 多个焊接接头（280）位于衬底和电子器件（290）之间，并形成衬底和电子器件（290）之间的连接。 柔性区域在将管芯附着到衬底（芯片连接）期间由于衬底和裸片之间的热失配加载而减小焊点所经历的变形程度。 焊点变形的这种减少降低了焊点会破裂的可能性。
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公开(公告)号：US20090242247A1
公开(公告)日：2009-10-01
申请号：US12079785
申请日：2008-03-28
CPC分类号： H05K1/0201 , H01L21/4807 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/06 , H05K3/107 , H05K3/205 , H05K3/388 , H05K3/4617 , H05K3/4629 , H05K3/4647 , H05K2201/0175 , H05K2201/0187 , H05K2201/0376 , H05K2201/096 , H05K2201/09881 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
摘要翻译： 描述了用于封装衬底和管芯间隔件的层或层。 层或层包括位于平面内并由金属通孔分开的多个陶瓷阱。 陶瓷井内的凹陷由介电填料材料占据。
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8.发明授权Method for fabricating package substrate and die spacer layers having a ceramic backbone 有权制造具有陶瓷骨架的封装衬底和管芯间隔层的方法公开(公告)号：US08186051B2
公开(公告)日：2012-05-29
申请号：US12079785
申请日：2008-03-28
IPC分类号： H05K3/02
CPC分类号： H05K1/0201 , H01L21/4807 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/06 , H05K3/107 , H05K3/205 , H05K3/388 , H05K3/4617 , H05K3/4629 , H05K3/4647 , H05K2201/0175 , H05K2201/0187 , H05K2201/0376 , H05K2201/096 , H05K2201/09881 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.
摘要翻译： 描述了用于制造用于封装衬底和管芯间隔件的层或层的方法。 在一个实施方案中，制造层或层以包括位于平面内的多个陶瓷阱并且由金属通孔隔开，陶瓷井中的凹陷被介电填料材料占据。
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9.发明申请Use of die backside films to modulate EOL coplanarity of thin packages while providing thermal capability and laser markability of packages 审中-公开使用模具背面薄膜来调节薄封装的EOL共面性，同时提供封装的热性能和激光标记能力公开(公告)号：US20110156283A1
公开(公告)日：2011-06-30
申请号：US12655283
申请日：2009-12-28
申请人： Shankar Ganapathysubramanian , Leonel R. Arana , Robert L. Sankman , Wen Janet Feng , Robert M. Nickerson
发明人： Shankar Ganapathysubramanian , Leonel R. Arana , Robert L. Sankman , Wen Janet Feng , Robert M. Nickerson
CPC分类号： H01L24/81 , H01L21/56 , H01L21/561 , H01L21/6836 , H01L23/295 , H01L23/3121 , H01L23/3157 , H01L23/562 , H01L2221/68327 , H01L2221/68377 , H01L2224/81002 , H01L2224/81193 , H01L2224/814 , H01L2224/81815 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/3511 , H01L2924/00
摘要： A microelectronic package comprises a die (110) having a front side (111) containing active circuitry (115) and a back side (112) opposite the front side and a film (120) on the back side of the die. The film has a thickness (121) of at least 20 micrometers, a Young's modulus of at least 10 GPa, and a post-cure glass transition temperature of at least 100° Celsius.
摘要翻译： 微电子封装包括具有包含有源电路（115）的前侧（111）和与前侧相对的后侧（112）的模具（110）和在模具背面的膜（120）。 膜具有至少20微米的厚度（121），至少10GPa的杨氏模量和至少100℃的后固化玻璃化转变温度。
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公开(公告)号：US20130341076A1
公开(公告)日：2013-12-26
申请号：US13987701
申请日：2013-08-22
IPC分类号： H05K1/02
CPC分类号： H05K1/0201 , H01L21/4807 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/06 , H05K3/107 , H05K3/205 , H05K3/388 , H05K3/4617 , H05K3/4629 , H05K3/4647 , H05K2201/0175 , H05K2201/0187 , H05K2201/0376 , H05K2201/096 , H05K2201/09881 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.
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