公开(公告)号：US20100276767A1

公开(公告)日：2010-11-04

申请号：US12432377

申请日：2009-04-29

申请人： Lianjun Liu ,  Douglas G. Mitchell

发明人： Lianjun Liu ,  Douglas G. Mitchell

IPC分类号： H01L29/84 ,  H01L21/26

CPC分类号： H04R19/005 ,  H01L29/84 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device.

摘要翻译： 一种器件包括衬底，微电子机械系统（MEMS）结构和电介质膜。 衬底具有第一侧和第二侧，第二侧与第一侧相对。 MEMS结构形成在衬底的第一侧上。 空腔形成在与MEMS结构直接相对的基板中。 空腔具有形成在第二侧上的开口。 电介质膜附着到基片的第二侧并完全覆盖开口。 在一个实施例中，MEMS结构是用于麦克风的隔膜。 另一实施例包括用于形成装置的方法。

公开(公告)号：US08158492B2

公开(公告)日：2012-04-17

申请号：US12432377

申请日：2009-04-29

申请人： Lianjun Liu ,  Douglas G. Mitchell

发明人： Lianjun Liu ,  Douglas G. Mitchell

IPC分类号： H01L21/00

CPC分类号： H04R19/005 ,  H01L29/84 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device.

摘要翻译： 一种器件包括衬底，微电子机械系统（MEMS）结构和电介质膜。 衬底具有第一侧和第二侧，第二侧与第一侧相对。 MEMS结构形成在衬底的第一侧上。 空腔形成在与MEMS结构直接相对的基板中。 空腔具有形成在第二侧上的开口。 电介质膜附着到基片的第二侧并完全覆盖开口。 在一个实施例中，MEMS结构是用于麦克风的隔膜。 另一实施例包括用于形成装置的方法。

公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US08685790B2

公开(公告)日：2014-04-01

申请号：US13397034

申请日：2012-02-15

申请人： Alan J. Magnus ,  Carl E. D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

发明人： Alan J. Magnus ,  Carl E. D. Acosta ,  Douglas G. Mitchell ,  Justin E. Poarch

IPC分类号： H01L21/00

CPC分类号： H01L23/36 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

摘要翻译： 提供了一种用于形成用于封装在半导体器件封装中的管芯的用于形成用于电和/或热的背面接触的方法和设备。 可以在半导体器件封装内容纳不同厚度的管芯。 本发明的实施例提供耦合到管芯的背面接触的导电基座，其中在将管芯封装在封装内之前执行耦合。 此外，耦合到半导体器件封装内的不同裸片的导电基座具有这样的厚度，使得每个导电基座可以暴露在封装的背面，而不会暴露或损坏任何封装的裸片的背面。 本发明的实施例提供了导电基座由导电或导热材料制成并且使用导电和/或导热粘合剂耦合到器件裸片接触。

公开(公告)号：US20130049217A1

公开(公告)日：2013-02-28

申请号：US13222143

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Jason R. Wright

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Jason R. Wright

IPC分类号： H01L21/768 ,  H01L23/538

CPC分类号： H01L23/49827 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 将一个或多个信号导管放置在随后嵌入封装的半导体器件封装中的保持器中。 信号管道的端部暴露，然后将信号导管用作通过封装通孔，在封装的底部和顶部上的互连或触点之间提供信号承载通路。 取决于应用的性质，可以提供各种几何形状和材料的支架。 此外，具有信号导管的多个保持器可以提供在单个封装中，以在例如系统级封装应用中提供更复杂的互连配置要求。

公开(公告)号：US06361675B1

公开(公告)日：2002-03-26

申请号：US09451552

申请日：1999-12-01

申请人： Timothy Lee Johnson ,  Joseph English ,  David Austin ,  George F. Carney ,  Kandis Mae Knoblauch ,  Douglas G. Mitchell

发明人： Timothy Lee Johnson ,  Joseph English ,  David Austin ,  George F. Carney ,  Kandis Mae Knoblauch ,  Douglas G. Mitchell

IPC分类号： C25D502

CPC分类号： C25D7/12

摘要： A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.

摘要翻译： 制造半导体部件的方法包括在衬底（270）上沉积第一导电层（675），在第一导电层上形成图案化电镀掩模（673），将第一电镀电极（250）耦合到第一导电层 导电层而不刺穿电镀掩模，并且将第二导电层电镀到第一导电层的部分上。 一种用于制造方法的电镀工具包括位于外堰（210）内的内堰（220），外堰边缘（211）上方的弹性构件（230），位于外堰 的外部堰和弹性构件，以及位于压力环和外部堰之间的多个阴极接触（250,251,252,253）。 衬底位于弹性构件和压力环之间。

公开(公告)号：US4927505A

公开(公告)日：1990-05-22

申请号：US386058

申请日：1989-07-28

申请人： Ravinder K. Sharma ,  Harry J. Geyer ,  Douglas G. Mitchell

发明人： Ravinder K. Sharma ,  Harry J. Geyer ,  Douglas G. Mitchell

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L24/11 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/13 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  Y10T428/12528

摘要： A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.

摘要翻译： 使用钛 - 氮化钨/钛 - 钨/金（TiWN / TiW / Au）封装互连金属化方案来提供与半导体衬底上的芯片级互连金属化的电接触。 TiWN / TiW / Au封装互连金属化方案提供了耐高温和提高半导体芯片的可靠性的良好的附着力和阻隔性能。 TiWN层对芯片级互连金属化和钝化层提供良好的附着力。 它还提供改进的阻挡性能，以防止其它金属原子通过其扩散。 TiW层对金金属层提供良好的附着力。 金凸块可以电镀到金层上并且在TAB封装中自动地粘合到带的导电引线上; 或在传统包装中与金层结合的导线。

公开(公告)号：US4880708A

公开(公告)日：1989-11-14

申请号：US215108

申请日：1988-07-05

申请人： Ravinder K. Sharma ,  Harry J. Geyer ,  Douglas G. Mitchell

发明人： Ravinder K. Sharma ,  Harry J. Geyer ,  Douglas G. Mitchell

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L24/11 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/13 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  Y10T428/12528 ,  Y10T428/12549 ,  Y10T428/12569

摘要： A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.

摘要翻译： 使用钛 - 氮化钨/钛 - 钨/金（TiWN / TiW / Au）封装互连金属化方案来提供与半导体衬底上的芯片级互连金属化的电接触。 TiWN / TiW / Au封装互连金属化方案提供了耐高温和提高半导体芯片的可靠性的良好的附着力和阻隔性能。 TiWN层对芯片级互连金属化和钝化层提供良好的附着力。 它还提供改进的阻挡性能，以防止其它金属原子通过其扩散。 TiW层对金金属层提供良好的附着力。 金凸块可以电镀到金层上并且在TAB封装中自动地粘合到带的导电引线上; 或在传统包装中与金层结合的导线。

公开(公告)号：US09123685B2

公开(公告)日：2015-09-01

申请号：US13942518

申请日：2013-07-15

申请人： Weng Foong Yap ,  Douglas G. Mitchell

发明人： Weng Foong Yap ,  Douglas G. Mitchell

IPC分类号： H01L21/00 ,  H01L23/367 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/367 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/17519 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00

摘要： Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes forming one or more redistribution layers over an encapsulated die having a frontside bond pad area and a frontside passivated non-bond pad area. The redistribution layers are formed to have a frontside opening over the non-bond pad area of the encapsulated die. A primary heat sink body is provided in the frontside opening and thermally coupled to the encapsulated die. A contact array is formed over the redistribution layers and is electrically coupled to a plurality bond pads located on the frontside bond pad area of the encapsulated die.

摘要翻译： 提供了用于制造微电子封装的微电子封装和方法。 在一个实施例中，该方法包括在具有前侧接合焊盘区域和前侧钝化的非接合焊盘区域的封装的管芯上形成一个或多个再分布层。 再分布层形成为在封装的管芯的非接合焊盘区域上方具有前端开口。 主要散热体设置在前侧开口中并热耦合到封装的模具。 接触阵列形成在再分布层之上并且电耦合到位于封装管芯的前侧接合焊盘区域上的多个接合焊盘。

公开(公告)号：US08283207B2

公开(公告)日：2012-10-09

申请号：US13043094

申请日：2011-03-08

申请人： Chandrasekaram Ramiah ,  Douglas G. Mitchell ,  Michael F. Petras ,  Paul W. Sanders

发明人： Chandrasekaram Ramiah ,  Douglas G. Mitchell ,  Michael F. Petras ,  Paul W. Sanders

IPC分类号： H01L21/44

CPC分类号： H01L24/82 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/522 ,  H01L23/525 ,  H01L24/24 ,  H01L24/25 ,  H01L24/94 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/94 ,  H01L2924/01018 ,  H01L2924/01021 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/82

摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

摘要翻译： 通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。