公开(公告)号：US08247909B2

公开(公告)日：2012-08-21

申请号：US12929549

申请日：2011-02-01

Applicant: Longqiang Zu ,  Yu-Yu Lin

Inventor： Longqiang Zu ,  Yu-Yu Lin

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L23/16 ,  H01L23/041 ,  H01L23/3128 ,  H01L23/66 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device with a cavity structure comprises: a carrier substrate; a first die having an active surface and the pads thereon; a back surface of the first die is disposed on the carrier substrate; a second die having a top surface and a back surface and a cavity structure therein; the top surface of a second die is flipped to dispose on the first die, and the cavity structure is an inverse U-type to dispose between the active surface of the first die and the top surface of the second die; the wires is electrically connected the pads with the first connecting points; a package body encapsulated the first die, the second die, the wires, and the portion of the top surface of the carrier substrate; and the connecting components is disposed on the back surface of the carrier substrate and is electrically connected the second connecting points.

Abstract translation: 具有空腔结构的半导体器件包括：载体衬底; 具有活性表面的第一模具和其上的焊盘; 第一管芯的背面设置在载体基板上; 具有顶表面和后表面的第二模具和其中的空腔结构; 翻转第二管芯的顶表面以配置在第一管芯上，并且空腔结构是配置在第一管芯的有效表面和第二管芯的顶表面之间的反U型; 所述电线将所述焊盘与所述第一连接点电连接; 包装体包封第一模具，第二模具，导线以及载体基板顶表面的部分; 并且连接部件设置在载体基板的背面上并与第二连接点电连接。

公开(公告)号：US20120146218A1

公开(公告)日：2012-06-14

申请号：US12929549

申请日：2011-02-01

Applicant: Longqiang Zu ,  Yu-Yu Lin

Inventor： Longqiang Zu ,  Yu-Yu Lin

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L23/16 ,  H01L23/041 ,  H01L23/3128 ,  H01L23/66 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device with a cavity structure comprises: a carrier substrate; a first die having an active surface and the pads thereon; a back surface of the first die is disposed on the carrier substrate; a second die having a top surface and a back surface and a cavity structure therein; the top surface of a second die is flipped to dispose on the first die, and the cavity structure is an inverse U-type to dispose between the active surface of the first die and the top surface of the second die; the wires is electrically connected the pads with the first connecting points; a package body encapsulated the first die, the second die, the wires, and the portion of the top surface of the carrier substrate; and the connecting components is disposed on the back surface of the carrier substrate and is electrically connected the second connecting points.

公开(公告)号：US06303871B1

公开(公告)日：2001-10-16

申请号：US09330648

申请日：1999-06-11

Applicant: Longqiang Zu ,  Huong Do

Inventor： Longqiang Zu ,  Huong Do

IPC: H05K702

CPC classification number: H05K1/0245 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/09681 ,  H05K2201/10674 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T428/24917 ,  H01L2924/00

Abstract: An organic land grid array having multiple built up layers of metal sandwiching non-conductive layers, having a staggered pattern of degassing holes in the metal layers. The staggered pattern occurs in two substantially perpendicular directions. Traces between the metal layers have reduced impedance variation due to the degassing hole pattern.

Abstract translation: 一种具有多层金属夹层非导电层的有机栅格阵列，在金属层中具有交错排列的脱气孔图案。 交错图案发生在两个基本垂直的方向上。 金属层之间的痕迹由于脱气孔图案而降低了阻抗变化。

公开(公告)号：US08152048B2

公开(公告)日：2012-04-10

申请号：US12331154

申请日：2008-12-09

Applicant: Longqiang Zu

Inventor： Longqiang Zu

IPC: B23K35/12

CPC classification number: B23K3/0638 ,  H01L2924/0002 ,  H05K3/1225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09018 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T428/24273 ,  Y10T428/24612 ,  H01L2924/00

Abstract: A multiple substrate system, a method, and structure for adapting solder volume to a warped module. An illustrative embodiment comprises a method for joining a first substrate to a second substrate. A deviation from a nominal gap between the first substrate and the second substrate at a first region of the first substrate is ascertained. A volume of solder paste necessary to compensate for the deviation from a nominal gap is determined. The volume of solder paste necessary to compensate for the deviation at the first region of the first substrate is applied. Further, the second substrate is bonded to the first substrate using, at least in part, the solder paste applied at the first region of the first substrate.

Abstract translation: 用于使焊料体积适应于翘曲模块的多基板系统，方法和结构。 示例性实施例包括用于将第一基板接合到第二基板的方法。 确定在第一基板的第一区域处与第一基板和第二基板之间的标称间隙的偏差。 确定补偿偏离标称间隙所需的一定量的焊膏。 施加补偿第一基板的第一区域的偏差所需的焊膏的体积。 此外，使用至少部分地施加在第一基板的第一区域处的焊膏，将第二基板接合到第一基板。

公开(公告)号：US20120021564A1

公开(公告)日：2012-01-26

申请号：US13064646

申请日：2011-04-06

Applicant: Chien-Wen Chen ,  Longqiang Zu ,  Chen-Fa Tsai

Inventor： Chien-Wen Chen ,  Longqiang Zu ,  Chen-Fa Tsai

IPC: H01L21/58

CPC classification number: H01L24/92 ,  H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29147 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/9211 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01019 ,  H01L2924/01077 ,  H05K3/3457 ,  H05K3/3494 ,  H05K2201/10159 ,  H05K2201/10674 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.

Abstract translation: 本发明提供了一种半导体器件的封装方法，其使用多次回流工艺来加热焊球以防止焊球的变形，从而可以提高制造工艺的成品率，并且半导体器件的可靠性可以 增加。

公开(公告)号：US08278145B2

公开(公告)日：2012-10-02

申请号：US13064646

申请日：2011-04-06

Applicant: Chien-Wen Chen ,  Longqiang Zu ,  Chen-Fa Tsai

Inventor： Chien-Wen Chen ,  Longqiang Zu ,  Chen-Fa Tsai

IPC: H01L21/44

CPC classification number: H01L24/92 ,  H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29147 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/9211 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01019 ,  H01L2924/01077 ,  H05K3/3457 ,  H05K3/3494 ,  H05K2201/10159 ,  H05K2201/10674 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.

公开(公告)号：US20100143656A1

公开(公告)日：2010-06-10

申请号：US12331154

申请日：2008-12-09

Applicant: Longqiang Zu

Inventor： Longqiang Zu

IPC: B32B3/10 ,  B23K1/00 ,  B23K31/12

CPC classification number: B23K3/0638 ,  H01L2924/0002 ,  H05K3/1225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09018 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T428/24273 ,  Y10T428/24612 ,  H01L2924/00

Abstract: A multiple substrate system, a method, and structure for adapting solder volume to a warped module. An illustrative embodiment comprises a method for joining a first substrate to a second substrate. A deviation from a nominal gap between the first substrate and the second substrate at a first region of the first substrate is ascertained. A volume of solder paste necessary to compensate for the deviation from a nominal gap is determined. The volume of solder paste necessary to compensate for the deviation at the first region of the first substrate is applied. Further, the second substrate is bonded to the first substrate using, at least in part, the solder paste applied at the first region of the first substrate.

Abstract translation: 用于使焊料体积适应于翘曲模块的多基板系统，方法和结构。 示例性实施例包括用于将第一基板接合到第二基板的方法。 确定在第一基板的第一区域处与第一基板和第二基板之间的标称间隙的偏差。 确定补偿偏离标称间隙所需的一定量的焊膏。 施加补偿第一基板的第一区域的偏差所需的焊膏的体积。 此外，使用至少部分地施加在第一基板的第一区域处的焊膏，将第二基板接合到第一基板。

公开(公告)号：US06177732B1

公开(公告)日：2001-01-23

申请号：US09322069

申请日：1999-05-27

Applicant: Longqiang Zu

Inventor： Longqiang Zu

IPC: H01L2348

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L2924/0002 ,  H05K1/114 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09709 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention is a method and apparatus to minimize via inductance in a multi-layer organic land grid array (OLGA) packaging. A plurality of layers are staggered vertically. The plurality of layers include first and second layers which have first and second metal strip connections, respectively. The second layer is above the first layer. The first metal strip connection is aligned with the second metal strip connection to maximize mutual inductance between the first and second layers.

Abstract translation: 本发明是一种在多层有机焊盘网格阵列（OLGA）封装中最小化通孔电感的方法和装置。 多层是垂直交错的。 多个层包括分别具有第一和第二金属条连接的第一和第二层。 第二层在第一层之上。 第一金属带连接与第二金属带连接对准以最大化第一和第二层之间的互感。