公开(公告)号：US20140120678A1

公开(公告)日：2014-05-01

申请号：US14063118

申请日：2013-10-25

申请人： Manabu Shinriki ,  Paul Brabant ,  Keith Chung, JR.

发明人： Manabu Shinriki ,  Paul Brabant ,  Keith Chung, JR.

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639

摘要： The present invention addresses the key challenges in FinFET fabrication, that is, the fabrications of thin, uniform fins and also reducing the source/drain series resistance. More particularly, this application relates to FinFET fabrication techniques utilizing tetrasilane to enable conformal deposition with high doping using phosphate, arsenic and boron as dopants thereby creating thin fins having uniform thickness (uniformity across devices) as well as smooth, vertical sidewalls, while simultaneously reducing the parasitic series resistance.

摘要翻译： 本发明解决了FinFET制造中的关键挑战，即薄的均匀散热片的制造，并且还减少了源/漏串联电阻。 更具体地说，本申请涉及利用四硅烷使磷酸盐，砷和硼作为掺杂剂进行高掺杂的保形沉积的FinFET制造技术，从而产生具有均匀厚度（均匀性的器件）以及平滑的垂直侧壁的薄翅片，同时减少 寄生串联电阻。

公开(公告)号：US20080081112A1

公开(公告)日：2008-04-03

申请号：US11540197

申请日：2006-09-29

申请人： Paul Brabant ,  Paul Jacobson

发明人： Paul Brabant ,  Paul Jacobson

IPC分类号： C23C16/00 ,  B05D3/06

CPC分类号： C30B25/10 ,  C30B23/06 ,  C30B35/00 ,  H01L21/67103 ,  H01L21/67115

摘要： A reactor for processing a plurality of workpieces including a support for holding the plurality of workpieces, a first processing zone, one or more radiant heating elements adapted to heat a plurality of workpieces positioned in the first processing zone, a second processing zone, one or more resistive heating elements adapted to heat a plurality of workpieces positioned in the second processing zone, and an apparatus for moving the support between the first processing zone and the second processing zone.

摘要翻译： 一种用于处理多个工件的反应器，包括用于保持多个工件的支撑件，第一处理区域，适于加热位于第一处理区域中的多个工件的一个或多个辐射加热元件，第二处理区域，一个或 适于加热位于第二处理区域中的多个工件的更多的电阻加热元件，以及用于在第一处理区域和第二处理区域之间移动支撑件的装置。

公开(公告)号：US20050092235A1

公开(公告)日：2005-05-05

申请号：US10993024

申请日：2004-11-18

申请人： Paul Brabant ,  Joseph Italiano ,  Chantal Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

发明人： Paul Brabant ,  Joseph Italiano ,  Chantal Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

IPC分类号： C30B1/00 ,  C30B23/00 ,  C30B25/00 ,  C30B25/02 ,  C30B28/12 ,  C30B28/14 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/36

CPC分类号： C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

摘要： Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.

摘要翻译： 用于沉积诸如外延Ge和SiGe膜的外延膜的方法。 在从高温加工冷却到含Ge层的较低沉积温度时，向基板提供Si或Ge化合物。 导致平滑，薄，相对缺陷的Ge或SiGe层。 还提供了轻松，高Ge含量种子层和上覆应变层之间的退化弛豫SiGe。

公开(公告)号：US08088225B2

公开(公告)日：2012-01-03

申请号：US12641712

申请日：2009-12-18

申请人： Matt G. Goodman ,  Jereon Stoutyesdijk ,  Ravinder Aggarwal ,  Mike Halpin ,  Tony Keeton ,  Mark Hawkins ,  Lee Haen ,  Armand Ferro ,  Paul Brabant ,  Robert Vyne ,  Gregory M. Bartlett ,  Joseph P. Italiano ,  Bob Haro

发明人： Matt G. Goodman ,  Jereon Stoutyesdijk ,  Ravinder Aggarwal ,  Mike Halpin ,  Tony Keeton ,  Mark Hawkins ,  Lee Haen ,  Armand Ferro ,  Paul Brabant ,  Robert Vyne ,  Gregory M. Bartlett ,  Joseph P. Italiano ,  Bob Haro

IPC分类号： C23C16/458 ,  C23C16/00 ,  H01L21/306

CPC分类号： H01L21/68735 ,  H01J37/32871 ,  H01L21/67028

摘要： A substrate support system comprises a substrate holder having a plurality of passages extending between top and bottom surfaces thereof. The substrate holder supports a peripheral portion of the substrate backside so that a thin gap is formed between the substrate and the substrate holder. A hollow support member provides support to an underside of, and is configured to convey gas upward into one or more of the passages of, the substrate holder. The upwardly conveyed gas flows into the gap between the substrate and the substrate holder. Depending upon the embodiment, the gas then flows either outward and upward around the substrate edge (to inhibit backside deposition of reactant gases above the substrate) or downward through passages of the substrate holder, if any, that do not lead back into the hollow support member (to inhibit autodoping by sweeping out-diffused dopant atoms away from the substrate backside).

摘要翻译： 衬底支撑系统包括具有在其顶表面和底表面之间延伸的多个通道的衬底保持器。 衬底保持器支撑衬底背面的周边部分，使得在衬底和衬底保持器之间形成薄的间隙。 中空的支撑构件为衬底的下侧提供支撑，并且构造成将气体向上输送到衬底保持器的一个或多个通道中。 向上输送的气体流入基板和基板支架之间的间隙。 根据实施例，气体然后围绕衬底边缘向外和向上流动（以阻止反应物气体在衬底上方的背面沉积）或向下穿过衬底保持器的通道（如果有的话），其不会引回到中空支撑件 （通过从扩散的掺杂​​剂原子远离衬底背面来抑制自掺杂）。

公开(公告)号：US20060234504A1

公开(公告)日：2006-10-19

申请号：US11343264

申请日：2006-01-30

申请人： Matthias Bauer ,  Chantal Arena ,  Ronald Bertram ,  Pierre Tomasini ,  Nyles Cody ,  Paul Brabant ,  Joseph Italiano ,  Paul Jacobson ,  Keith Weeks

发明人： Matthias Bauer ,  Chantal Arena ,  Ronald Bertram ,  Pierre Tomasini ,  Nyles Cody ,  Paul Brabant ,  Joseph Italiano ,  Paul Jacobson ,  Keith Weeks

IPC分类号： H01L21/44

CPC分类号： H01L29/7848 ,  C23C16/04 ,  C23C16/22 ,  C23C16/24 ,  C23C16/32 ,  C23C16/325 ,  C23C16/45512 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/32056 ,  H01L21/3215 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.

摘要翻译： 化学气相沉积方法使用丙硅烷和含卤素蚀刻剂源（例如氯）在混合基底的选定区域上选择性沉积含Si膜。 掺杂源可以与丙硅烷和蚀刻剂源混合以选择性沉积掺杂的含Si薄膜。 选择性沉积方法可用于各种应用，例如半导体制造。

公开(公告)号：US20060211248A1

公开(公告)日：2006-09-21

申请号：US11362461

申请日：2006-02-24

申请人： Paul Brabant ,  Paul Jacobson ,  Keith Weeks

发明人： Paul Brabant ,  Paul Jacobson ,  Keith Weeks

IPC分类号： H01L21/306 ,  H01L21/302 ,  C23F1/00

CPC分类号： C23F1/12 ,  C23C16/4402 ,  C23C16/4405 ,  H01J37/3244 ,  H01L21/67115

摘要： A method for purifying a gas stream in a semiconductor process system comprises cooling impurities in the gas stream. The gas stream may comprise an HCl gas having a moisture content. The moisture contacts a cold element onto which the moisture can condense.

摘要翻译： 在半导体工艺系统中净化气流的方法包括冷却气流中的杂质。 气流可以包含具有水分含量的HCl气体。 湿气会接触冷水元素，水分可以凝结在其上。

公开(公告)号：US20080017101A1

公开(公告)日：2008-01-24

申请号：US11867318

申请日：2007-10-04

申请人： Matthias Bauer ,  Paul Brabant ,  Trevan Landin

发明人： Matthias Bauer ,  Paul Brabant ,  Trevan Landin

IPC分类号： C30B23/06

CPC分类号： C30B25/186 ,  C30B25/10 ,  C30B25/183 ,  C30B29/08 ,  Y10S438/935

摘要： A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 Å. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.

摘要翻译： 一种方法包括在反应室中，在第一温度下在含硅表面上沉积锗种子层。 种子层的厚度在约一个单层和约一个之间。 该方法还包括在沉积种子层之后，在继续沉积锗的同时增加反应室的温度。 该方法还包括将反应室保持在第二温度范围内，同时继续沉积锗。 第二温度范围大于第一温度。

公开(公告)号：US20070224787A1

公开(公告)日：2007-09-27

申请号：US11388313

申请日：2006-03-23

申请人： Keith Weeks ,  Paul Brabant

发明人： Keith Weeks ,  Paul Brabant

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262

摘要： Some embodiments of the invention are related to manufacturing semiconductors. Methods and apparatuses are disclosed that provide thin and fully relaxed SiGe layers. In some embodiments, the presence of oxygen between a single crystal structure and a SiGe heteroepitaxial layer, and/or within the SiGe heteroepitaxial layer, allow the SiGe layer to be thin and fully relaxed. In some embodiments, a strained layer of Si can be deposited over the fully relaxed SiGe layer.

摘要翻译： 本发明的一些实施方案涉及制造半导体。 公开了提供薄且完全松弛的SiGe层的方法和装置。 在一些实施方案中，在单晶结构和SiGe异质外延层之间和/或SiGe异质外延层内的存在使SiGe层变薄并完全松弛。 在一些实施例中，Si的应变层可以沉积在完全松弛的SiGe层上。

公开(公告)号：US20060281322A1

公开(公告)日：2006-12-14

申请号：US11506320

申请日：2006-08-18

申请人： Paul Brabant ,  Joseph Italiano ,  Chantal Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

发明人： Paul Brabant ,  Joseph Italiano ,  Chantal Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

IPC分类号： H01L21/461

CPC分类号： C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

摘要： Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.

公开(公告)号：US20060201414A1

公开(公告)日：2006-09-14

申请号：US11433535

申请日：2006-05-12

申请人： Paul Brabant ,  Joe Italiano ,  Jianqing Wen

发明人： Paul Brabant ,  Joe Italiano ,  Jianqing Wen

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C23C16/4408 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/4405 ,  C30B25/02 ,  C30B25/18 ,  C30B29/30 ,  C30B31/00 ,  H01L21/02046 ,  H01L21/02052 ,  Y10T117/10 ,  Y10T117/1004 ,  Y10T117/1008

摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.