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    High-speed, high-sensitivity charge-coupled device with independent pixel control of charge collection and storage
    3.
    发明授权
    High-speed, high-sensitivity charge-coupled device with independent pixel control of charge collection and storage 有权
    高速，高灵敏度的电荷耦合器件，具有独立的像素控制电荷收集和存储

    公开(公告)号：US07091530B1

    公开(公告)日：2006-08-15

    申请号：US10612174

    申请日：2003-07-02

    申请人： Robert K. Reich ,  Bernard B. Kosicki ,  Jonathan C. Twichell ,  Barry E. Burke ,  Dennis D. Rathman

    发明人： Robert K. Reich ,  Bernard B. Kosicki ,  Jonathan C. Twichell ,  Barry E. Burke ,  Dennis D. Rathman

    IPC分类号： H01L27/148

    CPC分类号： H01L27/1485 ,  H01L27/1464 ,  H01L27/14812 ,  H01L31/035281

    摘要： A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the sequence of image frames. Each subpixel includes a doped photogenerated charge collection channel region opposite the illumination-accessible substrate surface, a charge collection channel region control electrode, doped charge drain regions adjacent to the channel region, a charge drain region control electrode, and a doped charge collection control region. To each subpixel are provided channel region and drain region control voltage connections, for independent collection and storage of photogenerated charge from the substrate at the charge collection channel region of a selected subpixel during one in the sequence of image frames and for drainage of photogenerated charge from the substrate to a drain region.

    摘要翻译： 一种电荷耦合器件成像器，其包括设置在半导体衬底中的超像素阵列，该半导体衬底具有可入射照明的表面。 对于每个超像素，提供多个子像素，每个子像素对应于图像帧序列中的一个。 每个子像素包括与照明可访问衬底表面相对的掺杂光生电荷收集通道区域，电荷收集通道区域控制电极，与沟道区相邻的掺杂电荷漏极区，电荷漏极区控制电极和掺杂电荷收集控制区 。 每个子像素都提供了沟道区域和漏极区域控制电压连接，用于在图像帧序列中的一个期间，从所选择的子像素的电荷收集通道区域处的基底在基底处独立收集和存储光生电荷，并且将光生电荷从 衬底到漏区。

    Barrier layer device processing
    4.
    发明授权
    Barrier layer device processing 失效
    屏障层设备处理

    公开(公告)号：US5198881A

    公开(公告)日：1993-03-30

    申请号：US742274

    申请日：1991-08-07

    申请人： Jammy C. Huang ,  Mordechai Rothschild ,  Barry E. Burke ,  Daniel J. Ehrlich ,  Bernard B. Kosicki

    发明人： Jammy C. Huang ,  Mordechai Rothschild ,  Barry E. Burke ,  Daniel J. Ehrlich ,  Bernard B. Kosicki

    IPC分类号： H01L27/148

    CPC分类号： H01L27/14831

    摘要： A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.

    摘要翻译： 在半导体膜器件上通过单步激光工艺形成表面电子势垒区域，其在高于透光深度的表面区域中产生尖锐的掺杂分布。 观察到增强的量子效率，并且通过选择性地形成不同深度的势垒层，实现了用于双色灵敏度的CCD器件结构。 阻挡层导致增强的膜型和辐射硬化的双极和CMOS器件。

    Low-light-level imaging and image processing
    5.
    发明授权
    Low-light-level imaging and image processing 失效
    低光级成像和图像处理

    公开(公告)号：US5880777A

    公开(公告)日：1999-03-09

    申请号：US632746

    申请日：1996-04-15

    申请人： Eugene D. Savoye ,  Allen M. Waxman ,  Robert K. Reich ,  Barry E. Burke ,  James A. Gregory ,  William H. McGonagle ,  Andrew H. Loomis ,  Bernard B. Kosicki ,  Robert W. Mountain ,  Alan N. Gove ,  David A. Fay ,  James E. Carrick

    发明人： Eugene D. Savoye ,  Allen M. Waxman ,  Robert K. Reich ,  Barry E. Burke ,  James A. Gregory ,  William H. McGonagle ,  Andrew H. Loomis ,  Bernard B. Kosicki ,  Robert W. Mountain ,  Alan N. Gove ,  David A. Fay ,  James E. Carrick

    IPC分类号： H01L27/148 ,  H04N5/20 ,  H04N5/335 ,  H04N5/351 ,  H04N5/361 ,  H04N5/372 ,  H04N5/225

    CPC分类号： H04N5/335 ,  H04N5/20 ,  H04N5/3696

    摘要： An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B. The output image frame sequence is characterized by noise-limited resolution of at least a minimum number, N.sub.M, of line pairs per millimeter, referred to the charge-coupled imaging device pixel array, in an imaged scene as a function of illuminance of the input light impinging the charge-coupled imaging device pixels.

    摘要翻译： 提供一种成像系统，用于对场景进行成像，以每秒至少约25幅图像帧的帧速率R产生场景的图像序列序列。 该系统包括光输入端口，电荷耦合成像装置，模拟信号处理器和模数转换器（A / D）。 A / D数字化放大的像素信号以产生格式化为多个数字像素值中的每一个的一系列图像帧并且具有由多个数字位B表示的数字像素值的动态范围的数字图像信号，其中 B大于8.提供数字图像处理器用于处理图像帧序列中的数字像素值以产生代表成像场景的帧速率R的输出图像帧序列，等待时间不超过 约1 / R和由数字比特数D表示的图像帧像素值的动态范围，其中D小于B.输出图像帧序列的特征在于噪声限制分辨率至少最小数目NM 被称为电荷耦合成像装置像素阵列的线对每毫米在成像场景中作为照射电荷耦合成像装置像素的输入光的照度的函数。

    Interconnection technique for hybrid integrated devices
    6.
    发明授权
    Interconnection technique for hybrid integrated devices 失效
    混合集成设备的互连技术

    公开(公告)号：US5904495A

    公开(公告)日：1999-05-18

    申请号：US873123

    申请日：1997-06-11

    申请人： Barry E. Burke ,  Bernard B. Kosicki

    发明人： Barry E. Burke ,  Bernard B. Kosicki

    IPC分类号： H01L27/146 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00 ,  H01L21/30 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L27/14634 ,  H01L27/14601 ,  H01L27/1464 ,  H05K3/4038 ,  H05K3/4611 ,  Y10S438/977

    摘要： A hybrid integrated circuit and method of fabricating a hybrid integrated circuit. A first wafer is provided having a first surface with a first electrical contact for a first active circuit associated therewith and a second surface. A second wafer is provided having a third surface with a second electrical contact for a second active circuit associated therewith and a fourth surface, the second wafer being chemically thinned at the fourth surface. The first and second wafers are bonded together at an interface between the first and third surfaces such that the first and second electrical contacts are relatively aligned with one another. The fourth surface of the second wafer is processed to define an access via to both the first and second contacts. An electrical interconnection is formed between the first and second contacts within the access via so that the first and second active circuits are electrically interconnected.

    摘要翻译： 一种混合集成电路及其制造方法。 提供第一晶片，其具有第一表面，其具有用于与其相关联的第一有源电路的第一电触点和第二表面。 提供第二晶片，其具有第三表面，其具有用于与其相关联的第二有源电路的第二电触点和第四表面，所述第二晶片在第四表面处化学稀释。 第一和第二晶片在第一和第三表面之间的界面处结合在一起，使得第一和第二电触点彼此相对对准。 处理第二晶片的第四表面以限定通过第一和第二触点的通路。 在接入通路内的第一和第二触点之间形成电互连，使得第一和第二有源电路电互连。

    Fabrication of a high-precision blooming control structure for an image sensor
    7.
    发明授权
    Fabrication of a high-precision blooming control structure for an image sensor 失效

    公开(公告)号：US07074639B2

    公开(公告)日：2006-07-11

    申请号：US10023387

    申请日：2001-12-17

    申请人： Barry E. Burke ,  Eugene D. Savoye

    发明人： Barry E. Burke ,  Eugene D. Savoye

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14887

    摘要： Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate. The blooming barrier region is of a conductivity type and level that is selected based on the blooming barrier width to produce a corresponding electrical potential barrier between the charge collection and blooming drain regions. The blooming barrier regions of the structure are very precisely defined by the selected acute blooming barrier impurity implantation angle, and optionally in addition by a rotation of the blooming barrier impurity implantation, as well as a non-vertical sidewall profile of the an impurity implantation masking layer.

    Electronic shutter with photogenerated charge extinguishment capability for back-illuminated image sensors
    8.
    发明授权
    Electronic shutter with photogenerated charge extinguishment capability for back-illuminated image sensors 有权
    具有背光照明图像传感器的具有光生电荷灭能能力的电子快门

    公开(公告)号：US08536625B2

    公开(公告)日：2013-09-17

    申请号：US12878082

    申请日：2010-09-09

    申请人： Barry E. Burke

    发明人： Barry E. Burke

    IPC分类号： H01L27/148

    CPC分类号： H01L27/14812 ,  H01L27/14868

    摘要： An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array. A substrate bulk region between the shutter buried layer and the photogenerated-charge-extinguishment layer is characterized by an electrical resistivity enabling independent electrical bias of the photogenerated-charge-extinguishment layer from electrically-doped regions of the substrate.

    摘要翻译： 电子图像传感器包括具有被配置为接受照射到设置在基板中的像素阵列的照明的第一表面的半导体基板。 用于每个像素的电掺杂沟道区域设置在与第一衬底表面相对的第二衬底表面处。 通道区域用于在基板中收集光生电荷。 电掺杂沟道阻挡区位于每个沟道区之间的第二衬底表面。 在第二衬底表面的深度处设置在衬底中的电子掺杂快门掩埋层大于像素沟道区的深度延伸穿过像素阵列。 在第一衬底表面处的电掺杂光生电荷 - 消光层延伸穿过像素阵列。 快门掩埋层和光生电荷 - 灭弧层之间的衬底主体区域的特征在于电阻率使得光生电荷 - 灭弧层与衬底的电掺杂区域具有独立的电偏压。

    Multidirectional transfer charge-coupled device
    9.
    发明授权
    Multidirectional transfer charge-coupled device 失效
    多向传输电荷耦合器件

    公开(公告)号：US5760431A

    公开(公告)日：1998-06-02

    申请号：US708610

    申请日：1996-09-05

    申请人： Eugene D. Savoye ,  Barry E. Burke ,  John Tonry

    发明人： Eugene D. Savoye ,  Barry E. Burke ,  John Tonry

    IPC分类号： H01L27/148 ,  H01L29/10 ,  H01L29/768

    CPC分类号： H01L29/76858 ,  H01L27/1464 ,  H01L27/14831 ,  H01L29/1062

    摘要： A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

    摘要翻译： 一种配置在电荷存储介质中的多向电荷转移装置。 该装置包括电荷存储区域的阵列。 每个所述电荷存储区域包括多个第一栅极，每个第一栅极布置在每个电荷存储区域的第一部分中，多个第二栅极，每个第二栅极布置在每个电荷存储区域的第二部分中， 多个第三栅极，每个第三栅极布置在每个电荷存储区域的第三部分中，以及多个第四栅极，每个栅极布置在每个电荷存储区域的第四部分中。 多个栅极和电荷存储区被配置为限定相对于彼此非共线的至少三个双向电荷传输路径。 多个栅极被顺序地偏置以沿着所述双向电荷转移路径之一建立电荷转移，并形成阻挡电位以在剩余电荷转移路径中进行电荷转移。

    High-yield single-level gate charge-coupled device design and fabrication
    10.
    发明授权
    High-yield single-level gate charge-coupled device design and fabrication 有权
    高产量单级栅极电荷耦合器件的设计与制造

    公开(公告)号：US07217601B1

    公开(公告)日：2007-05-15

    申请号：US10691080

    申请日：2003-10-22

    申请人： Barry E. Burke ,  Vyshnavi Suntharalingam

    发明人： Barry E. Burke ,  Vyshnavi Suntharalingam

    IPC分类号： H01L21/339 ,  H01L21/00 ,  H01L21/8238

    CPC分类号： H01L29/66954 ,  H01L29/768

    摘要： In accordance with the invention, an electrically conducting charge transfer channel is formed in a semiconductor substrate and an electrically insulating layer is formed on a surface of the substrate; a layer of gate electrode material is formed on the insulating layer. On the gate material layer is formed a first patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gate electrodes, and the first-pattern-exposed regions of the gate material layer are electrically doped. In addition, on the gate material layer is formed a second patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gaps between gate electrodes, and the second-pattern-exposed regions of the gate material layer are etched.

    摘要翻译： 根据本发明，在半导体衬底中形成导电电荷传输沟道，并且在衬底的表面上形成电绝缘层; 在绝缘层上形成一层栅电极材料。 在栅极材料层上形成第一图案化掩模层，该掩模层具有暴露下面的栅极材料层的区域以形成栅电极，并且栅极材料层的第一图案曝光区域被电掺杂的孔。 此外，在栅极材料层上形成具有孔的第二图案化掩模层，其具有暴露栅极材料层的下部栅极材料层的区域，以形成栅电极之间的间隙，栅极材料层的第二图案曝光区域被蚀刻 。