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    Semiconductor embedded layer technology utilizing selective epitaxial growth methods
    1.
    发明授权
    Semiconductor embedded layer technology utilizing selective epitaxial growth methods 失效
    采用选择性外延生长方法的半导体嵌入层技术

    公开(公告)号：US5032538A

    公开(公告)日：1991-07-16

    申请号：US073912

    申请日：1987-07-07

    申请人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    发明人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    IPC分类号： H01L21/20 ,  H01L21/335 ,  H01L21/74 ,  H01L23/482 ,  H01L23/52 ,  H01L23/535 ,  H01L29/772 ,  H01L29/92

    CPC分类号： H01L29/66424 ,  H01L21/743 ,  H01L23/4824 ,  H01L23/52 ,  H01L23/535 ,  H01L28/40 ,  H01L29/7722 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/026 ,  Y10S148/053 ,  Y10S148/115 ,  Y10S148/142 ,  Y10S148/164

    摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).A method of fabricating this transistor as well as methods for forming integrated circuit structures are also disclosed. Metal and other layers may be selectively embedded in semiconductor crystal. Embedded metal layers may serve as interconnections between devices. Devices may be in a stacked configuration.

    摘要翻译： 公开了一种可渗透的基极晶体管（30），其包括嵌入半导体晶体（32）中以分离集电极（38）和发射极（40）区域并形成肖特基势垒的金属基底层（34）。 金属基层具有至少一个开口（37），晶体半导体（32）通过该开口连接集电极（38）和发射极（40）区域。 欧姆接触（42,44）制成发射极（38）和集电极（40）区域。 基底层（34）中的所有开口（37）的宽度为与开口中的载流子浓度相对应的零偏置耗尽宽度的量级。 金属层（34）的厚度为该零偏置耗尽宽度的10％量级。 结果，每个开口中的势垒限制了偏压范围下部的电流。 随着正向基极偏压的增加，开口中比基底层（34）的金属低的电位被充分降低，从而可以显着增加从集电器（38）到发射极（40）的阻挡限制电流， 。 还公开了一种制造该晶体管的方法以及用于形成集成电路结构的方法。 金属等层可以选择性地嵌入在半导体晶体中。 嵌入式金属层可用作器件之间的互连。 设备可能处于堆叠配置。

    Semiconductor embedded layer technology including permeable base transistor
    4.
    发明授权
    Semiconductor embedded layer technology including permeable base transistor 失效
    半导体嵌入层技术包括可渗透晶体管

    公开(公告)号：US5298787A

    公开(公告)日：1994-03-29

    申请号：US678670

    申请日：1991-04-01

    申请人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    发明人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    IPC分类号： H01L21/20 ,  H01L21/335 ,  H01L21/74 ,  H01L23/482 ,  H01L23/52 ,  H01L23/535 ,  H01L29/772 ,  H01L29/92 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00 ,  H01L29/30

    CPC分类号： H01L21/02532 ,  H01L21/02395 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/743 ,  H01L23/4824 ,  H01L23/52 ,  H01L23/535 ,  H01L28/40 ,  H01L29/66424 ,  H01L29/7722 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is diclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).

    摘要翻译： 包含嵌入在半导体晶体（32）中以分离集电极（38）和发射极（40）区域并与其形成肖特基势垒的金属基极层（34）的可渗透基极晶体管（30）被断开。 金属基层具有至少一个开口（37），晶体半导体（32）通过该开口连接集电极（38）和发射极（40）区域。 欧姆接触（42,44）制成发射极（38）和集电极（40）区域。 基底层（34）中的所有开口（37）的宽度为与开口中的载流子浓度相对应的零偏置耗尽宽度的量级。 金属层（34）的厚度为该零偏置耗尽宽度的10％量级。 结果，每个开口中的势垒限制了偏压范围下部的电流。 随着正向基极偏压的增加，开口中比基底层（34）的金属低的电位被充分降低，从而可以显着增加从集电器（38）到发射极（40）的阻挡限制电流， 。

    Method and system for distribution of an exposure control signal for focal plane arrays
    5.
    发明授权
    Method and system for distribution of an exposure control signal for focal plane arrays 有权
    用于焦平面阵列曝光控制信号分配的方法和系统

    公开(公告)号：US07501634B1

    公开(公告)日：2009-03-10

    申请号：US10742285

    申请日：2003-12-19

    申请人： Robert K. Reich ,  Bernard Kosicji ,  Dennis Rathman ,  Richard Osgood ,  Michael Rose ,  R. Allen Murphy ,  Robert Berger

    发明人： Robert K. Reich ,  Bernard Kosicji ,  Dennis Rathman ,  Richard Osgood ,  Michael Rose ,  R. Allen Murphy ,  Robert Berger

    IPC分类号： H01L27/146

    CPC分类号： H04N5/2353 ,  H01L27/14609 ,  H01L27/14643 ,  H04N5/353

    摘要： A large format imager includes an array of pixels for converting electromagnetic radiation into electrical signals and a trigger to from an optical pulse so as to trigger the pixels to generate an integration period. Each pixel includes a photodiode to convert light intensity of high-frequency radiation into an electrical charge, a reset switch to reset the photodiode, circuitry to enable sampling of the electrical charge produced by the photodiode, a photoswitch to convert an optical trigger pulse, received from the trigger, into an electrical signal, an inverter to produce a control signal corresponding to the electrical signal produced by the photoswitch, and control circuitry to locally generate integration control signals. The integration control signals control a start of an integration period for the photodiode, duration of the integration period for the photodiode, and the sampling of the electrical charge produced by the photodiode. The large format imager may also include a trigger for producing an electrical pulse so as to trigger the pixels to generate an integration period and tree type electrical distribution system for propagating the electrical pulse to all the pixels, wherein each pixel includes a global repeater circuit to propagate a first edge of said electrical pulse along said tree type electrical distribution system and a local repeater circuit to provide a local array of pixels with the first edge of the electrical pulse.

    摘要翻译： 大格式成像器包括用于将电磁辐射转换为电信号的像素阵列和来自光脉冲的触发，以便触发像素以产生积分周期。 每个像素包括光电二极管以将高频辐射的光强度转换为电荷，复位开关以复位光电二极管，电路以使得能够对由光电二极管产生的电荷进行采样，光接收器转换光接收脉冲 从触发器转换成电信号，逆变器产生对应于由光开关产生的电信号的控制信号，以及控制电路以本地产生积分控制信号。 积分控制信号控制光电二极管的积分周期的开始，光电二极管的积分周期的持续时间以及由光电二极管产生的电荷的采样。 大格式成像器还可以包括用于产生电脉冲的触发器，以便触发像素以产生积分周期，并且用于将电脉冲传播到所有像素的树型配电系统，其中每个像素包括全局中继器电路 沿着所述树型配电系统和本地中继器电路传播所述电脉冲的第一边缘，以向电脉冲的第一边缘提供局部阵列阵列。

    Semiconductor embedded layer technology including permeable base transistor, fabrication method
    8.
    发明授权
    Semiconductor embedded layer technology including permeable base transistor, fabrication method 失效
    半导体嵌入层技术包括可渗透晶体管，制造方法

    公开(公告)号：US4378629A

    公开(公告)日：1983-04-05

    申请号：US65514

    申请日：1979-08-10

    申请人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    发明人： Carl O. Bozler ,  Gary D. Alley ,  William T. Lindley ,  R. Allen Murphy

    IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/335 ,  H01L21/74 ,  H01L23/482 ,  H01L23/52 ,  H01L23/535 ,  H01L29/10 ,  H01L29/772 ,  H01L29/80 ,  H01L29/92 ,  H01L21/95

    CPC分类号： H01L29/66424 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/743 ,  H01L23/4824 ,  H01L23/52 ,  H01L23/535 ,  H01L28/40 ,  H01L29/7722 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/164

    摘要： A layer of material such as the metal base of a transistor is embedded in single crystal. A layer of the material with small, uniformly dimensioned and uniformly spaced openings is formed on a single crystal substrate, and the single crystal is grown from the exposed portions of the substrate over the layer of material. For best results, the layer of material to be embedded is deposited relative to the crystal orientation to provide a much greater rate of crystal growth laterally across the layer than away from the crystal substrate. The method is particularly useful in fabricating a permeable base transistor having slits formed in the metal base layer. An integrated circuit can be fabricated by forming a pattern of conductive material on a single crystal, that pattern having continuous regions which inhibit further crystal growth and narrow regions or regions having openings therein which permit lateral crystal growth across those regions. In that way, the conductive pattern is selectively embedded with the continuous regions left exposed after crystal growth. Connections can be made between the exposed regions and a pattern on the new crystal layer. This method has particular usefulness in fabricating multi-level integrated circuits.

    摘要翻译： 诸如晶体管的金属基底的材料层被嵌入在单晶中。 在单晶衬底上形成具有小的，均匀尺寸和均匀间隔的开口的材料层，并且单晶从衬底层的暴露部分生长在材料层上。 为了获得最佳结果，相对于晶体取向沉积要嵌入的材料层，以提供横跨层的晶体生长比离开晶体衬底的更大的晶体生长速率。 该方法在制造具有形成在金属基底层中的狭缝的可渗透的基极晶体管中特别有用。 可以通过在单晶上形成导电材料图案来制造集成电路，该图案具有抑制进一步晶体生长的连续区域，并且具有允许在这些区域上横向晶体生长的窄区域或其中具有开口的区域。 以这种方式，导电图案被选择性地嵌入在晶体生长后留下的连续区域。 可以在曝光区域和新晶体层上的图案之间进行连接。 该方法在制造多电平集成电路中具有特别的用途。