公开(公告)号：US20080203565A1

公开(公告)日：2008-08-28

申请号：US12114238

申请日：2008-05-02

申请人： Yoichiro KURITA ,  Masaya Kawano ,  Koji Soejima

发明人： Yoichiro KURITA ,  Masaya Kawano ,  Koji Soejima

IPC分类号： H01L23/498

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83051 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H05K3/4644 ,  H05K3/4676 ,  H05K3/4688 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

摘要： The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.

摘要翻译： 半导体器件1包括互连层10,20，IC芯片30，经由插头42,44，密封树脂50和焊球60。 互连层10包括通孔塞42。 通孔插头42在互连层20一侧的端面的面积比相对端面即IC芯片30一侧的端面小。 通孔插头44在互连层10一侧的端面的面积小于相对端面，即焊球60一侧的端面。 构成互连层10的绝缘树脂14的热分解温度高于构成互连层20的绝缘树脂24的热分解温度。

公开(公告)号：US20100087058A1

公开(公告)日：2010-04-08

申请号：US12635160

申请日：2009-12-10

申请人： Koji SOEJIMA ,  Yoichiro KURITA ,  Masaya KAWANO ,  Shintaro YAMAMICHI ,  Katsumi KIKUCHI

发明人： Koji SOEJIMA ,  Yoichiro KURITA ,  Masaya KAWANO ,  Shintaro YAMAMICHI ,  Katsumi KIKUCHI

IPC分类号： H01L21/60

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

摘要翻译： 第一电子电路部件和第二电子电路部件分别经由第一焊料和第二焊料电连接到导电部件。 导电构件形成在树脂膜中。 导电构件被构造成包含第二扩散阻挡金属膜。 第二扩散阻挡金属膜防止第二焊料的扩散。 在导电构件和第一焊料之间设置有第一扩散阻挡金属膜。 第一扩散阻挡金属膜防止第一焊料的扩散。 在树脂膜的第一表面和导电部件上形成粘接金属膜，以与树脂膜和导电部件接触。 粘合金属膜比第一焊料和第一扩散阻挡金属膜中的任一种具有比树脂膜更强的粘附性。

公开(公告)号：US20080079164A1

公开(公告)日：2008-04-03

申请号：US11865750

申请日：2007-10-02

申请人： Yoichiro KURITA ,  Koji Soejima ,  Masaya Kawano

发明人： Yoichiro KURITA ,  Koji Soejima ,  Masaya Kawano

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/3128 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

摘要翻译： 电子设备包括第一互连层和第二互连层。 第二互连层设置在第一互连层的下表面上。 第一互连层包括通孔插头（第一导电插头）。 通孔塞在第二互连层一侧的端面的面积小于相对端面。 通孔插头暴露在面向第二互连层的第一互连层的表面上。 形成第一互连层的绝缘树脂的热分解温度高于形成第二互连层的绝缘树脂。

公开(公告)号：US20100297811A1

公开(公告)日：2010-11-25

申请号：US12853660

申请日：2010-08-10

申请人： Masaya KAWANO ,  Koji SOEJIMA ,  Yoichiro KURITA

发明人： Masaya KAWANO ,  Koji SOEJIMA ,  Yoichiro KURITA

IPC分类号： H01L21/50 ,  H01L21/768

CPC分类号： H05K3/423 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/113 ,  H05K1/114 ,  H05K3/025 ,  H05K3/064 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

摘要翻译： 根据本发明的实施例的制造方法包括在支撑衬底70上形成种子金属层20a，在种子金属层20a上形成包括互连18的互连层10，在形成互连之后移除支撑衬底70 层10，并且图案化种子金属层20a，从而在去除支撑衬底之后形成互连20。

公开(公告)号：US20110075389A1

公开(公告)日：2011-03-31

申请号：US12960148

申请日：2010-12-03

申请人： Shintaro YAMAMICHI ,  Katsumi KIKUCHI ,  Yoichiro KURITA ,  Koji SOEJIMA

发明人： Shintaro YAMAMICHI ,  Katsumi KIKUCHI ,  Yoichiro KURITA ,  Koji SOEJIMA

IPC分类号： H01R9/00

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board. Connections for very small wiring are thereby made possible, and a plurality of semiconductor elements can be very densely connected.

摘要翻译： 一种半导体器件，包括平面布线板，布置在所述布线板的一个表面上的第一LSI，用于覆盖所述一个表面的密封树脂和所述第一半导体元件的侧面，以及设置在所述布线的另一个表面上的第二LSI 板。 布线基板具有作为布线层的导电布线，作为布线层的支撑层的绝缘树脂，以及穿过布线层和支撑层的导电性通孔。 半导体元件的外周边缘从上方垂直观察到的焊盘的内部的位置之间的连接点，其中所述焊盘从形成有外部连接端子的焊盘部分选择，并且形成了布线板 在与地面相同的平面中，不均匀地分布在布线板的一侧。 由此，可以实现非常小的布线的连接，并且可以非常密集地连接多个半导体元件。

公开(公告)号：US20100127405A1

公开(公告)日：2010-05-27

申请号：US12618399

申请日：2009-11-13

申请人： Katsumi KIKUCHI ,  Shintaro YAMAMICHI ,  Yoichiro KURITA ,  Koji SOEJIMA

发明人： Katsumi KIKUCHI ,  Shintaro YAMAMICHI ,  Yoichiro KURITA ,  Koji SOEJIMA

IPC分类号： H01L23/48 ,  H05K1/11 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

摘要翻译： 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US20090224387A1

公开(公告)日：2009-09-10

申请号：US12466994

申请日：2009-05-15

申请人： Masaya KAWANO ,  Tsutomu TASHIRO ,  Yoichiro KURITA

发明人： Masaya KAWANO ,  Tsutomu TASHIRO ,  Yoichiro KURITA

IPC分类号： H01L23/00 ,  H01L23/52

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L23/564 ,  H01L2224/32145

摘要： The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A1 provided in the silicon layer 16. An insulating region 18 is provided on the semiconductor substrate 10. The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A1.

摘要翻译： 半导体芯片1具有半导体基板10.在本实施方式中，作为SOI基板的半导体基板10由支撑基板12，形成在支撑基板12上的层叠结构的绝缘层14构成， 以及形成在具有层状结构的绝缘层14上的硅层16。 半导体衬底10具有设置在硅层16中的电路形成区域A.绝缘区域18设置在半导体衬底10上。绝缘区域18设置成围绕电路形成区域A1的整个侧面。

公开(公告)号：US20110089561A1

公开(公告)日：2011-04-21

申请号：US12906377

申请日：2010-10-18

申请人： Yoichiro KURITA ,  Masaya KAWANO

发明人： Yoichiro KURITA ,  Masaya KAWANO

IPC分类号： H01L23/48

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/60 ,  H01L24/24 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

摘要翻译： 半导体封装具有：第一芯片; 和第二芯片。 第一芯片具有：形成在第一芯片的主表面上的绝缘树脂层; 在所述绝缘树脂层的区域中形成为贯通所述绝缘树脂层并电连接到所述第二芯片的凸点状的第一内部电极组， 用于与外部设备电连接的外部电极组; 和与外部电极组电连接的静电放电保护元件组。 第一内部电极组不与静电放电保护元件组电连接。

公开(公告)号：US20070278698A1

公开(公告)日：2007-12-06

申请号：US11834094

申请日：2007-08-06

申请人： Yoichiro KURITA

发明人： Yoichiro KURITA

IPC分类号： H01L23/52

CPC分类号： H01L21/76256 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an SOI substrate, is constituted by comprising an insulating layer 34, and a silicon layer 36, which is provided on the insulating layer 34, including a circuit forming region A1. The insulating layer 34 functions as a protective film (a first protective film) covering a lower face (a face opposite to the semiconductor chip 10) of the circuit forming region A1. A protective film 38 (a second protective film) is provided on the semiconductor substrate 22. The protective film 38 covers a side face of the circuit forming region A1.

摘要翻译： 半导体器件1具有半导体芯片10（第一半导体芯片）和半导体芯片20（第二半导体芯片）。 半导体芯片20形成在半导体芯片10上。 半导体芯片20由半导体基板22构成。 作为SOI衬底的半导体衬底22由包括电路形成区域A 1的绝缘层34和设置在绝缘层34上的硅层36构成。 绝缘层34用作覆盖电路形成区域A 1的下表面（与半导体芯片10相对的面）的保护膜（第一保护膜）。 在半导体基板22上设置保护膜38（第二保护膜）。 保护膜38覆盖电路形成区域A 1的侧面。

公开(公告)号：US20120322204A1

公开(公告)日：2012-12-20

申请号：US13595416

申请日：2012-08-27

申请人： Yoichiro KURITA

发明人： Yoichiro KURITA

IPC分类号： H01L21/50 ,  H01L21/283

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105

摘要： A method of manufacturing a semiconductor device includes preparing a semiconductor element including a main surface over which a wiring layer is formed, forming a seed layer over the main surface, forming a resist layer over the main surface such that the resist layer covers the seed layer, removing a part of the resist layer by exposing and developing the resist layer, in which a part of the wiring layer is exposed from the removed part of the resist layer, forming a plurality of conductive posts electrically connected to the wiring layer at the removed part of the resist layer, forming a solder layer at each top of the plurality of conductive posts, removing a residual resist layer over the main surface, removing an area other than an area which overlaps with the seed layer, and melting the solder layer and forming a surface shape.

摘要翻译： 一种制造半导体器件的方法包括制备半导体元件，该半导体元件包括主表面，在该主表面上形成布线层，在主表面上形成晶种层，在主表面上形成抗蚀剂层，使得抗蚀剂层覆盖种子层 通过曝光和显影抗蚀剂层来去除一部分抗蚀剂层，其中一部分布线层从抗蚀剂层的去除部分露出，形成多个导电柱，该导电柱电连接到去除的布线层 抗蚀剂层的一部分，在多个导电柱的每个顶部形成焊料层，在主表面上除去残留的抗蚀剂层，除去与种子层重叠的区域以外的区域，并熔化焊料层， 形成表面形状。