公开(公告)号：USH1153H

公开(公告)日：1993-03-02

申请号：US646834

申请日：1991-01-28

申请人： Melvin C. August ,  Diane M. Christie ,  Arthur J. Hebert ,  Eugene F. Neumann ,  Richard R. Steitz

发明人： Melvin C. August ,  Diane M. Christie ,  Arthur J. Hebert ,  Eugene F. Neumann ,  Richard R. Steitz

IPC分类号： H01L23/057 ,  H01L23/10 ,  H01L23/498

CPC分类号： H01L23/10 ,  H01L23/057 ,  H01L23/4985 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/16152

摘要： A hermetically sealed carrier for integrated circuits has an IC placed on a carrier substrate, and an electrical lead apparatus, comprised of a highly heat resistant substrate with a metallized interconnect pattern deposited thereon, connected to the IC and brought out across and over the edges of the carrier substrate to facilitate electrical connection to a circuit board. A lid is provided which is placed over the IC. A low-melting temperature adhesive means is then placed on the lid-to-carrier interface and is exposed to heat hermetically sealing the IC. A hermetically sealed carrier including a single silicon die which includes both an active region where an integrated circuit may be fabricated and an inactive region is also provided. Electrical leads are electrically interconnected to the IC of the active region and extend to the periphery of the inactive region of the silicon die. A lid and adhesive means is provided for hermetically sealing the IC of the active region.

公开(公告)号：US5358826A

公开(公告)日：1994-10-25

申请号：US884285

申请日：1992-05-08

申请人： Richard R. Steitz ,  Diane M. Christie ,  Eugene F. Neumann ,  Melvin C. August ,  Stephen Nelson

发明人： Richard R. Steitz ,  Diane M. Christie ,  Eugene F. Neumann ,  Melvin C. August ,  Stephen Nelson

IPC分类号： H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  G03F7/00

CPC分类号： H01L23/13 ,  H01L21/4846 ,  H01L23/49866 ,  H01L23/5386 ,  H01L2924/0002 ,  Y10S257/915

摘要： A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

摘要翻译： 描述了从晶片状基板同时制造金属化载体的方法，其中这种晶片状基板允许使用标准IC制造装置和方法。 因此，可以沉积非常薄且精细尺寸的迹线。 使用薄膜制造技术来在芯片载体的表面上产生高密度迹线，从而允许从IC直接连接到载体的外围，而不需要通孔。 盖子密封并保护包装。 痕迹由多个金属组成以便于粘合，每个金属对于痕迹的一部分是均匀的。 迹线的一个金属部分是与放置在载体中的IC芯片兼容的类型。 迹线的另一金属部分是与印刷电路板上的迹线相兼容的类型。 在金属之间插入金属阻挡层，以防止金属从一种金属扩散到另一种金属的邻接部分。

公开(公告)号：US5182420A

公开(公告)日：1993-01-26

申请号：US506729

申请日：1990-04-09

申请人： Richard R. Steitz ,  Diane M. Christie ,  Eugene F. Neumann ,  Melvin C. August ,  Stephen Nelson

发明人： Richard R. Steitz ,  Diane M. Christie ,  Eugene F. Neumann ,  Melvin C. August ,  Stephen Nelson

IPC分类号： H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/13 ,  H01L21/4846 ,  H01L23/49866 ,  H01L23/5386 ,  H01L2924/0002 ,  Y10S257/915

摘要： A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

摘要翻译： 描述了从晶片状基板同时制造金属化载体的方法，其中这种晶片状基板允许使用标准IC制造装置和方法。 因此，可以沉积非常薄且精细尺寸的迹线。 使用薄膜制造技术来在芯片载体的表面上产生高密度迹线，从而允许从IC直接连接到载体的外围，而不需要通孔。 盖子密封并保护包装。 痕迹由多个金属组成以便于粘合，每个金属对于痕迹的一部分是均匀的。 迹线的一个金属部分是与放置在载体中的IC芯片兼容的类型。 迹线的另一金属部分是与印刷电路板上的迹线相兼容的类型。 在金属之间插入金属阻挡层，以防止金属从一种金属扩散到另一种金属的邻接部分。

公开(公告)号：US5127570A

公开(公告)日：1992-07-07

申请号：US545271

申请日：1990-06-28

申请人： Richard R. Steitz ,  Melvin C. August ,  Diane M. Christie ,  Deanna M. Dowdle ,  Dean B. Dudley ,  Stephen E. Nelson ,  Eugene F. Neumann ,  Paul E. Schroeder

发明人： Richard R. Steitz ,  Melvin C. August ,  Diane M. Christie ,  Deanna M. Dowdle ,  Dean B. Dudley ,  Stephen E. Nelson ,  Eugene F. Neumann ,  Paul E. Schroeder

IPC分类号： B23K26/00 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/36 ,  H05K3/40

CPC分类号： H01L24/86 ,  B23K26/0661 ,  B23K26/382 ,  B23K26/384 ,  B23K26/386 ,  B23K26/40 ,  B23K26/402 ,  H01L23/4985 ,  H05K3/4084 ,  B23K2201/35 ,  B23K2203/05 ,  B23K2203/08 ,  B23K2203/10 ,  B23K2203/12 ,  B23K2203/172 ,  B23K2203/42 ,  B23K2203/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/118 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2203/1184 ,  H05K3/0032 ,  H05K3/361 ,  Y10T29/49133

摘要： A flexible automated bonding apparatus electrically interconnects integrated circuit carriers, printed circuit boards, and other devices. A metallized interconnect pattern is deposited on the surface of the substrate. The metallized interconnects in the pattern span apertures created in the substrate using an excimer laser. Thus, the metallized interconnects can be electrically bonded through the apertures to elements lying underneath the substrate.

摘要翻译： 柔性自动接合装置将集成电路载体，印刷电路板和其它装置电互连。 金属化互连图案沉积在基板的表面上。 图案中的金属化互连使用准分子激光器跨越在衬底中产生的孔。 因此，金属化互连可以通过孔电连接到位于衬底下方的元件。

公开(公告)号：US4949453A

公开(公告)日：1990-08-21

申请号：US366604

申请日：1989-06-15

申请人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

发明人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/64

CPC分类号： H01L23/5382 ,  H01L23/49838 ,  H01L23/647 ,  H01L24/50 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/3011 ,  Y10T29/49099 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

摘要翻译： 描述了通用芯片载体，其包括连接在载波上的电压总线和信号迹线之间的电压总线和多个终端电阻的组成部分。 电压总线缠绕在芯片载体上，从而提供大面积的金属。 通过选择性地使用终端电阻器，可以为特定类型的集成电路定制通用载波，即信号的源或目的地终止。 可以通过用标准电探针施加的电流尖峰“终止”端接电阻来定制信号迹线。 备用接合焊盘和终端电阻器以围绕载体周边的间隔放置，作为对有缺陷或错误去除的终端电阻器的保险。

公开(公告)号：US5122620A

公开(公告)日：1992-06-16

申请号：US722364

申请日：1991-06-25

申请人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

发明人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/64

CPC分类号： H01L23/647 ,  H01L23/49838 ,  H01L23/5382 ,  H01L24/50 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/3011

摘要： A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "operating" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

摘要翻译： 描述了通用芯片载体，其包括连接在载波上的电压总线和信号迹线之间的电压总线和多个终端电阻的组成部分。 电压总线缠绕在芯片载体上，从而提供大面积的金属。 通过选择性地使用终端电阻器，可以为特定类型的集成电路定制通用载波，即信号的源或目的地终止。 可以通过由标准电探针施加的电流尖峰“终止”终端电阻来定制信号迹线。 备用接合焊盘和终端电阻器以围绕载体周边的间隔放置，作为对有缺陷或错误去除的终端电阻器的保险。

公开(公告)号：US5258576A

公开(公告)日：1993-11-02

申请号：US816967

申请日：1992-01-03

申请人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

发明人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L23/02

CPC分类号： H01L23/647 ,  H01L23/49838 ,  H01L23/5382 ,  H01L24/50 ,  H01L2224/32225 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/3011

摘要： A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

摘要翻译： 描述了通用芯片载体，其包括连接在载波上的电压总线和信号迹线之间的电压总线和多个终端电阻的组成部分。 电压总线缠绕在芯片载体上，从而提供大面积的金属。 通过选择性地使用终端电阻器，可以为特定类型的集成电路定制通用载波，即信号的源或目的地终止。 可以通过用标准电探针施加的电流尖峰“终止”端接电阻来定制信号迹线。 备用接合焊盘和终端电阻器以围绕载体周边的间隔放置，作为对有缺陷或错误去除的终端电阻器的保险。

公开(公告)号：USRE34395E

公开(公告)日：1993-10-05

申请号：US804958

申请日：1991-12-11

申请人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

发明人： Eugene F. Neumann ,  Melvin C. August ,  James N. Kruchowski ,  Stephen Nelson ,  Richard R. Steitz

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01C17/06

CPC分类号： H01L23/49838 ,  H01L23/498 ,  H01L23/5382 ,  H01L23/647 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  Y10T29/49099 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "opening" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

公开(公告)号：US5134247A

公开(公告)日：1992-07-28

申请号：US313395

申请日：1989-02-21

申请人： Peter J. Wehner ,  Paul M. Knudsen ,  David F. Leonard ,  Richard R. Steitz ,  David L. Duxstad ,  Melvin C. August ,  Delvin D. Eberlein

发明人： Peter J. Wehner ,  Paul M. Knudsen ,  David F. Leonard ,  Richard R. Steitz ,  David L. Duxstad ,  Melvin C. August ,  Delvin D. Eberlein

IPC分类号： H01L23/10 ,  H01L23/13 ,  H01L23/64

CPC分类号： H01L24/49 ,  H01L23/10 ,  H01L23/13 ,  H01L23/642 ,  H01L2224/48091 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A ceramic chip carrier package for integrated circuits is described which provides reduced interlead capacitance. A cavity for the placement of the integrated circuit chip is centrally located on a substrate. The leads of the package are bridged between the cavity and the outer periphery of the substrate. The leads are bonded to the substrate using adhesive glass placed on the substrate at the outer periphery of the cavity and at the outer periphery of the substrate. Sealing glass is placed on the outer periphery of the substrate over the leads to provide a bonding material for a lid to the package. The area between the cavity and the outer periphery of the substrate has no adhesive or sealing glass which thus provides an air dielectric between the leads so that interlead capacitance is reduced. In a second preferred embodiment, a channel is provided in the ceramic substrate between the periphery of the cavity and the periphery of the substrate to control the flow of adhesive glass and sealing glass so that the glasses do not migrate onto the leads. Since the air dielectric constant is lower than the glass dielectric constant, the interlead capacitance is lower than that found in prior art packages.

摘要翻译： 描述了用于集成电路的陶瓷芯片载体封装，其提供降低的交错电容。 用于放置集成电路芯片的空腔位于基板的中心。 封装的引线桥接在腔体和衬底的外周边之间。 引线使用位于空腔的外周和衬底的外周的位于衬底上的粘合剂玻璃粘合到衬底上。 将密封玻璃放置在引线上的基板的外周上，以提供用于封装的盖的接合材料。 空腔与衬底的外周之间的区域没有粘合剂或密封玻璃，因此在引线之间提供空气电介质，从而降低了交错电容。 在第二优选实施例中，在陶瓷基板中在空腔的周边和基板的周边之间设置通道，以控制粘合剂玻璃和密封玻璃的流动，使得玻璃不会迁移到引线上。 由于空气介电常数低于玻璃介电常数，所以交错电容比现有技术封装中低。

公开(公告)号：US4984993A

公开(公告)日：1991-01-15

申请号：US351871

申请日：1989-05-12

申请人： Eugene F. Neumann ,  Melvin C. August ,  Stephen A. Bowen

发明人： Eugene F. Neumann ,  Melvin C. August ,  Stephen A. Bowen

IPC分类号： H01R12/89 ,  H01R13/193

CPC分类号： H01R12/89 ,  H01R13/193

摘要： An electrical end connector (10) of the zero insertion force type includes a pair of opposing blocks (21, 40), one of which blocks is slideably mounted in a housing (22). Opposite corresponding pairs of female receptacles (34) and male pins (31) are cooperatively mounted on the opposing blocks (21, 40). The housig (22) has two sets of oppositely disposed windows formed through the longitudinal ends. One block (40) has a channel formed therethrough, such that the block (40) is urged transversely upon insertion of a cam-like slider device (70), thereby selectively engaging or disengaging the male pins (31) and female receptacles (43).

摘要翻译： 零插入力型的电端连接器（10）包括一对相对的块（21,40），其中一个块可滑动地安装在壳体（22）中。 相对的相对的阴插座（34）和阳销（31）相对地配合安装在相对的块（21,40）上。 椅子（22）具有通过纵向端部形成的两组相对设置的窗口。 一个块（40）具有穿过其形成的通道，使得块（40）在插入凸轮状滑块装置（70）时被横向推动，从而选择性地接合或分离阳销（31）和阴插座（43） ）。