利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.018 秒)

    System and Method for Efficient Drive of Capacitive Actuators with Voltage Amplification
    2.
    发明申请
    System and Method for Efficient Drive of Capacitive Actuators with Voltage Amplification 有权
    具有电压放大功能的电容式驱动器的高效驱动系统和方法

    公开(公告)号：US20140217930A1

    公开(公告)日：2014-08-07

    申请号：US14236437

    申请日：2012-08-06

    申请人： Michael Karpelson ,  Robert J Wood ,  Gu-Yeon Wei

    发明人： Michael Karpelson ,  Robert J Wood ,  Gu-Yeon Wei

    IPC分类号： H02P31/00

    CPC分类号： H02P31/00 ,  F02D41/2096 ,  F02D2041/2013 ,  F02D2041/2051 ,  H02M3/33576 ,  H02M3/3372 ,  H02M2001/009 ,  H02N2/06 ,  H02N2/067

    摘要： A circuit for driving a plurality of capacitive actuators, the circuit having a low-voltage side, a high voltage side and a flyback transformer between the two. The low-voltage side comprises first and second pairs of low-side switches connected in series across an input voltage. The flyback transformer has a primary winding connected to the two pairs of switches. The high-voltage side has a pair of switches connected between the secondary winding of the flyback transformer and a ground and a plurality of capacitive loads and bidirectional switches to connect the loads to the secondary winding of the flyback transformer and a ground.

    摘要翻译： 用于驱动多个电容性致动器的电路，该电路在两者之间具有低压侧，高压侧和回扫变压器。 低电压侧包括跨输入电压串联连接的第一和第二对低侧开关。 回扫变压器具有连接到两对开关的初级绕组。 高压侧具有连接在回扫变压器的次级绕组与接地之间的一对开关和多个容性负载和双向开关，以将负载连接到回扫变压器的次级绕组和地。

    ULTRA LOW POWER SYSTEM FOR SENSOR NETWORK APPLICATIONS
    4.
    发明申请
    ULTRA LOW POWER SYSTEM FOR SENSOR NETWORK APPLICATIONS 审中-公开
    用于传感器网络应用的超低功率系统

    公开(公告)号：US20070214374A1

    公开(公告)日：2007-09-13

    申请号：US11685721

    申请日：2007-03-13

    申请人： Mark Hempstead ,  Nikhil Tripathi ,  Patrick Mauro ,  Gu-Yeon Wei ,  David Brooks

    发明人： Mark Hempstead ,  Nikhil Tripathi ,  Patrick Mauro ,  Gu-Yeon Wei ,  David Brooks

    IPC分类号： G06F1/00

    CPC分类号： H04W52/028 ,  H04W84/18 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/22

    摘要： A system for sensor network applications comprising a microcontroller for handling irregular events, at least one hardware accelerator for handling regular events, an event processor for interrupt handling and power management in the system, and a system bus. The microcontroller, hardware accelerator, and event processor each are connected to the system bus. The event processor gates power to the microcontroller to provide power to the microcontroller only for processing related to irregular events requiring processing by the microcontroller. The event processor further may gate power to the hardware accelerator. The system may further include a message processor and a plurality of sensors.

    摘要翻译： 一种用于传感器网络应用的系统，包括用于处理不规则事件的微控制器，用于处理常规事件的至少一个硬件加速器，用于系统中的中断处理和电源管理的事件处理器以及系统总线。 微控制器，硬件加​​速器和事件处理器都连接到系统总线。 事件处理器为微控制器提供电源，以向微控制器供电，仅用于与需要微控制器处理的不规则事件有关的处理。 事件处理器还可以对硬件加速器进行门电源。 系统还可以包括消息处理器和多个传感器。

    Adaptive event-guided system and method for avoiding voltage emergencies
    5.
    发明授权
    Adaptive event-guided system and method for avoiding voltage emergencies 有权
    自适应事件引导系统和避免电压紧急情况的方法

    公开(公告)号：US08949666B2

    公开(公告)日：2015-02-03

    申请号：US13201110

    申请日：2010-02-11

    申请人： Vijay Janapa Reddi ,  Meeta Sharma Gupta ,  Glenn Holloway ,  Gu-Yeon Wei ,  Michael D. Smith ,  David Brooks

    发明人： Vijay Janapa Reddi ,  Meeta Sharma Gupta ,  Glenn Holloway ,  Gu-Yeon Wei ,  Michael D. Smith ,  David Brooks

    IPC分类号： G06F11/00 ,  G06F1/28

    CPC分类号： G06F1/28

    摘要： In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

    摘要翻译： 在优选实施例中，本发明是用于避免电压紧急情况的系统。 该系统包括微处理器，用于节流微处理器的致动器，电压紧急检测器和电压紧急预报器。 电压应急检测器可以包括例如检查点恢复机构或传感器。 优选实施例的电压应急预测器包括用于跟踪控制流程指令和微架构事件的装置，用于存储引起电压紧急情况的电压紧急签名的装置，用于将电流控制流和微架构事件与存储的电压紧急签名进行比较以预测电压紧急情况的装置，以及 用于致动所述致动器以节制所述微处理器以避免预测的电压紧急情况的装置。

    Process Variation Tolerant Circuit With Voltage Interpolation And Variable Latency
    6.
    发明申请
    Process Variation Tolerant Circuit With Voltage Interpolation And Variable Latency 失效
    具有电压插补和可变延迟的过程变差容限电路

    公开(公告)号：US20090134707A1

    公开(公告)日：2009-05-28

    申请号：US12261771

    申请日：2008-10-30

    申请人： Xiaoyao Liang ,  David Brooks ,  Gu-Yeon Wei

    发明人： Xiaoyao Liang ,  David Brooks ,  Gu-Yeon Wei

    IPC分类号： H02J1/00

    CPC分类号： H02J1/10 ,  H03K5/135 ,  H03K2005/00065 ,  H03K2005/0011 ,  Y10T307/696

    摘要： A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits. The first voltage differs from the second voltage and the plurality of pipelined stages interpolates between the first and second voltages to provide differing effective voltages between the first and second voltages.

    摘要翻译： 具有动态可控功率的电路。 电路包括多个流水线级，每个流水线级包括两个时钟域，多个开关电路，每个开关电路连接到一个流水线级，第一和第二电源连接到多个流水线 通过开关电路的级，提供第一电压的第一电源和提供第二电压的第二电源，其中第一和第二电源各自可以独立于其它流水线级施加到流水线级，第一和第二补充时钟 以及连接到第一和第二互补时钟和多个流水线级的多个锁存器，用于证明基于锁存器的时钟以控制第一和第二时钟域并且能够跨越多个开关电路进行时间借用。 第一电压与第二电压不同，并且多个流水线级在第一和第二电压之间内插，以在第一和第二电压之间提供不同的有效电压。

    ADAPTIVE EVENT-GUIDED SYSTEM AND METHOD FOR AVOIDING VOLTAGE EMERGENCIES
    8.
    发明申请
    ADAPTIVE EVENT-GUIDED SYSTEM AND METHOD FOR AVOIDING VOLTAGE EMERGENCIES 有权
    用于避免电压紧急情况的自适应事件导向系统和方法

    公开(公告)号：US20120005515A1

    公开(公告)日：2012-01-05

    申请号：US13201110

    申请日：2010-02-11

    申请人： Vijay Janapa Reddi ,  Meeta Sharma Gupta ,  Glenn Holloway ,  Gu-Yeon Wei ,  Michael D. Smith ,  David Brooks

    发明人： Vijay Janapa Reddi ,  Meeta Sharma Gupta ,  Glenn Holloway ,  Gu-Yeon Wei ,  Michael D. Smith ,  David Brooks

    IPC分类号： G06F11/30

    CPC分类号： G06F1/28

    摘要： In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

    摘要翻译： 在优选实施例中，本发明是用于避免电压紧急情况的系统。 该系统包括微处理器，用于节流微处理器的致动器，电压紧急检测器和电压紧急预报器。 电压应急检测器可以包括例如检查点恢复机构或传感器。 优选实施例的电压应急预测器包括用于跟踪控制流程指令和微架构事件的装置，用于存储引起电压紧急情况的电压紧急签名的装置，用于将电流控制流和微架构事件与存储的电压紧急签名进行比较以预测电压紧急情况的装置，以及 用于致动所述致动器以节制所述微处理器以避免预测的电压紧急情况的装置。

    Process variation tolerant circuit with voltage interpolation and variable latency
    9.
    发明授权
    Process variation tolerant circuit with voltage interpolation and variable latency 失效
    具有电压内插和可变延迟的过程变差容限电路

    公开(公告)号：US07667497B2

    公开(公告)日：2010-02-23

    申请号：US12261771

    申请日：2008-10-30

    申请人： Xiaoyao Liang ,  David Brooks ,  Gu-Yeon Wei

    发明人： Xiaoyao Liang ,  David Brooks ,  Gu-Yeon Wei

    IPC分类号： H03K19/00

    CPC分类号： H02J1/10 ,  H03K5/135 ,  H03K2005/00065 ,  H03K2005/0011 ,  Y10T307/696

    摘要： A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits. The first voltage differs from the second voltage and the plurality of pipelined stages interpolates between the first and second voltages to provide differing effective voltages between the first and second voltages.

    摘要翻译： 具有动态可控功率的电路。 电路包括多个流水线级，每个流水线级包括两个时钟域，多个开关电路，每个开关电路连接到一个流水线级，第一和第二电源连接到多个流水线 通过开关电路的级，提供第一电压的第一电源和提供第二电压的第二电源，其中第一和第二电源各自可以独立于其它流水线级施加到流水线级，第一和第二补充时钟 以及连接到第一和第二互补时钟和多个流水线级的多个锁存器，用于证明基于锁存器的时钟以控制第一和第二时钟域并且能够跨越多个开关电路进行时间借用。 第一电压与第二电压不同，并且多个流水线级在第一和第二电压之间内插，以在第一和第二电压之间提供不同的有效电压。