公开(公告)号：US20180277509A1

公开(公告)日：2018-09-27

申请号：US15988351

申请日：2018-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Toyohiro Aoki ,  Takashi Hisada ,  Eiji Nakamura ,  Kuniaki Sueoka

IPC: H01L23/00 ,  B23K3/06 ,  B23K35/02 ,  H01L21/56 ,  B23K1/00

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K3/0623 ,  B23K3/0638 ,  B23K35/0238 ,  B23K35/0244 ,  H01L21/565 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/11312 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/94 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure.

公开(公告)号：US20120028412A1

公开(公告)日：2012-02-02

申请号：US13195128

申请日：2011-08-01

Applicant: Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC: H01L21/50 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Abstract translation: 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US10037967B1

公开(公告)日：2018-07-31

申请号：US15454229

申请日：2017-03-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Toyohiro Aoki ,  Takashi Hisada ,  Eiji Nakamura ,  Kuniaki Sueoka

IPC: H01L23/00 ,  H01L21/56 ,  B23K3/06 ,  B23K1/00 ,  B23K35/02

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K3/0623 ,  B23K3/0638 ,  B23K35/0238 ,  B23K35/0244 ,  H01L21/565 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/11312 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/94 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for depositing material on a chip include forming a mold layer on a substrate. The mold layer has one or more openings over respective contact areas on the substrate. The one or more openings are formed from an upper volume and a lower volume, the upper volume having a smaller diameter than a diameter of the lower volume. A material is injected into the one or more openings under pressure, such that gas trapped in the one or more openings displaces into the lower volume until the injected material in the one or more openings makes contact with each respective contact area.

公开(公告)号：US20070026631A1

公开(公告)日：2007-02-01

申请号：US11461416

申请日：2006-07-31

Applicant: Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

Inventor： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC: H01L21/76

CPC classification number: H01L24/12 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05683 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48673 ,  H01L2224/48683 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

Abstract translation: 一种电路部件，包括半导体衬底，所述半导体衬底上的衬垫，在侧壁上的含钽层和所述焊盘的底表面，所述半导体衬底上的钝化层，所述钝化层中的露出所述衬垫的开口， 由所述开口暴露在所述垫上的含钛层，以及在所述含钛层上方的金层。

公开(公告)号：US20180019219A1

公开(公告)日：2018-01-18

申请号：US15545670

申请日：2015-02-25

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Kyu Oh Lee

IPC: H01L23/00 ,  B23K35/26 ,  H01L23/498 ,  C22C13/00 ,  C22C19/03

CPC classification number: H01L24/05 ,  B23K35/262 ,  C22C13/00 ,  C22C19/03 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05564 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/0568 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81444 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

公开(公告)号：US20110266680A1

公开(公告)日：2011-11-03

申请号：US13180479

申请日：2011-07-11

Applicant: Mou-Shiung Lin ,  Chien-Kang Chou ,  Hsin-Jung Lo

Inventor： Mou-Shiung Lin ,  Chien-Kang Chou ,  Hsin-Jung Lo

IPC: H01L23/532 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2221/1094 ,  H01L2224/02166 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/451 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099

Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.

Abstract translation: 本发明提出了一种电路部件结构，其包括半导体衬底，形成在半导体衬底上并具有至少一个金属焊盘的细线金属化结构，形成在细线金属化结构上的钝化层，金属焊盘暴露 通过钝化层的开口，形成在细线金属化结构上的至少一个碳纳米管层和钝化层并与金属焊盘连接。 本发明提供一种碳纳米管回路部件结构及其制造方法，其中，半导体元件的电路由导电性碳纳米管构成，能够使半导体元件的电路变得更细且更致密 通过优异的导电性，柔性和碳纳米管的强度。

公开(公告)号：US07833894B2

公开(公告)日：2010-11-16

申请号：US11781746

申请日：2007-07-23

Applicant: W. Mark Hiatt

Inventor： W. Mark Hiatt

IPC: H01L29/40 ,  H01L21/00 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05683 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof are passivated and coated with a conductive material. A vent hole is then formed from the opposite surface to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and conductive material at both the active surface and the thinned back side. A metal layer having a glass transition temperature greater than that of the solder may be plated to form a dam structure covering one or both ends of the TWI. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

Abstract translation: 一种用于在衬底中形成透晶片互连（TWI）的方法。 盲孔由表面形成，其侧壁被钝化并涂覆有导电材料。 然后从相对表面形成通气孔以与盲孔相交。 盲孔被焊料填充，随后使晶片的通气孔部分的背面变薄至最终的基板厚度，以在活性表面和减薄的背面两者露出焊料和导电材料。 可以镀覆玻璃化转变温度高于焊料的金属层，以形成覆盖TWI的一端或两端的坝结构。 还公开了半导体器件，半导体器件和系统的中间结构。

公开(公告)号：US20070045779A1

公开(公告)日：2007-03-01

申请号：US11218705

申请日：2005-09-01

Applicant: W. Hiatt

Inventor： W. Hiatt

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05683 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof passivated and coated with a solder-wetting material. A vent hole is then formed from the opposite surface (e.g., wafer back side) to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and solder-wetting material at both the active surface and the thinned back side. A metal layer such as nickel, having a glass transition temperature greater than that of the solder, may be plated to form a dam structure covering one or both ends of the TWI including the solder and solder-wetting material to prevent leakage of molten solder from the TWI during high temperature excursions. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.

Abstract translation: 一种用于在衬底中形成厚度超过诸如半导体晶片的半导体管芯的厚度的贯穿晶片互连（TWI）的方法。 盲孔由活性表面形成，其侧壁钝化并涂覆有焊料润湿材料。 然后从相对表面（例如，晶片背面）形成通气孔以与盲孔相交。 盲孔被焊料填充，随后使晶片的通气孔部分的背面变薄至最终的基板厚度，以在活性表面和变薄的背面暴露焊料和焊料润湿材料。 可以镀覆玻璃化转变温度高于焊料的金属层，以形成覆盖TWI的一端或两端的坝结构，包括焊料和焊料润湿材料，以防止熔融焊料从 TWI在高温偏移期间。 还公开了半导体器件，半导体器件和系统的中间结构。

公开(公告)号：US11869870B1

公开(公告)日：2024-01-09

申请号：US17953697

申请日：2022-09-27

Applicant: SiTime Corporation

Inventor： Paul M. Hagelin ,  Charles I. Grosjean

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0381 ,  H01L2224/03826 ,  H01L2224/056 ,  H01L2224/05124 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05683 ,  H01L2224/08148 ,  H01L2224/80048 ,  H01L2224/80097 ,  H01L2224/80805 ,  H01L2224/83048 ,  H01L2224/83143 ,  H01L2224/83355 ,  H01L2224/83895 ,  H01L2224/83911 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1461

Abstract: First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.

公开(公告)号：US08749021B2

公开(公告)日：2014-06-10

申请号：US11964015

申请日：2007-12-25

Applicant: Mou-Shiung Lin ,  Gu-Yeon Wei

Inventor： Mou-Shiung Lin ,  Gu-Yeon Wei

IPC: H01L27/08 ,  H01L27/11 ,  H01L29/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H02M3/00 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L27/0605 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05683 ,  H01L2224/0603 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2924/01049 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

Abstract translation: 本发明揭示了半导体芯片结构及其应用电路网络，其中开关电压调节器或转换器通过芯片制造方法与半导体芯片集成，使得半导体芯片具有在特定电压范围内调节电压的能力。 因此，当印刷电路板（PCB）上放置许多不同工作电压的电气设备时，只需要构建一定数量的半导体芯片。 最初，为了解决电压的不同要求，需要增加不同输出电压的电源单元或各种电压调节器。 然而，使用内置的电压调节器或转换器，电压范围可以立即调整到所需的电压范围。 这种改进允许更容易地控制不同工作电压的电气设备并减少电气设备的响应时间。