公开(公告)号：US20150137125A1

公开(公告)日：2015-05-21

申请号：US14589547

申请日：2015-01-05

Applicant: Renesas Electronics Corporation

Inventor： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

Abstract translation: 提供了能够防止半导体装置的最上层的保护膜的破裂的技术，提高了半导体装置的可靠性。 在半导体芯片的主表面上形成的接合焊盘为矩形，并且在每个接合焊盘上的保护膜中形成开口，使得保护膜在每个接合的引线接合区域中的重叠宽度 衬垫比每个焊盘的探针区域中的保护膜的重叠宽度宽。

公开(公告)号：US20160336244A1

公开(公告)日：2016-11-17

申请号：US15219254

申请日：2016-07-25

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US20190057913A1

公开(公告)日：2019-02-21

申请号：US16167492

申请日：2018-10-22

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/00 ,  G01R31/26

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US09911673B2

公开(公告)日：2018-03-06

申请号：US15494501

申请日：2017-04-22

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US09165845B2

公开(公告)日：2015-10-20

申请号：US14465975

申请日：2014-08-22

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  G01R31/26

CPC classification number: H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract translation: 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US10134648B2

公开(公告)日：2018-11-20

申请号：US15876833

申请日：2018-01-22

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  G01R31/26

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US20180145001A1

公开(公告)日：2018-05-24

申请号：US15876833

申请日：2018-01-22

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US09824944B2

公开(公告)日：2017-11-21

申请号：US15280618

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

公开(公告)号：US20160035636A1

公开(公告)日：2016-02-04

申请号：US14876787

申请日：2015-10-06

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K999/99 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract translation: 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US10566255B2

公开(公告)日：2020-02-18

申请号：US16519150

申请日：2019-07-23

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L23/00 ,  H01L21/66 ,  G01R31/26 ,  H01L25/065

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.