Chip Cooling System with Convex Portion
    1.
    发明申请
    Chip Cooling System with Convex Portion 审中-公开
    带凸部的芯片冷却系统

    公开(公告)号:US20090109628A1

    公开(公告)日:2009-04-30

    申请号:US11928165

    申请日:2007-10-30

    IPC分类号: H01L23/367 F28F7/00

    摘要: Integrated circuit chip cooling methods and systems are disclosed. A method for cooling an integrated circuit chip may comprise: providing a cooling mechanism; positioning an interface medium between the cooling mechanism and the integrated circuit chip; and interfacing the cooling mechanism and the integrated circuit chip through the interface medium; wherein at least one of the cooling mechanism, the integrated circuit chip, or the interface medium includes a convex portion on an interface surface thereof.

    摘要翻译: 公开了集成电路芯片的冷却方法和系统。 用于冷却集成电路芯片的方法可以包括:提供冷却机构; 在冷却机构和集成电路芯片之间定位界面介质; 并通过接口介质与冷却机构和集成电路芯片接口; 其中所述冷却机构,所述集成电路芯片或所述界面介质中的至少一个在其界面表面上包括凸部。

    High power microjet cooler
    6.
    发明授权
    High power microjet cooler 失效
    大功率微型喷墨冷却器

    公开(公告)号:US07536870B2

    公开(公告)日:2009-05-26

    申请号:US11308504

    申请日:2006-03-30

    IPC分类号: F28D5/00

    摘要: A distribution apparatus, system and method for thermal control whereby a plate of a manifold assembly has predetermined surface features positioned on specific locations on a surface thereof for enhancing the cooling capabilities of the assembly. The predetermined surface features of the plate delay a velocity decay of a fluid impinging the surface of the plate, while also increase the surface area of the plate exposed to the impinging liquid, which in turn, maximize both the reliability and thermal performance of the overall thermal system at a given maximum operating pressure.

    摘要翻译: 一种用于热控制的分配设备,系统和方法,其中歧管组件的板具有定位在其表面上的特定位置上的预定表面特征,以增强组件的冷却能力。 板的预定表面特征延迟了撞击板表面的流体的速度衰减,同时还增加了暴露于冲击液体的板的表面积,这进而使整体的可靠性和热性能最大化 热系统在给定的最大工作压力。

    Low strain chip removal apparatus
    7.
    发明授权
    Low strain chip removal apparatus 有权
    低应变片去除装置

    公开(公告)号:US06745932B2

    公开(公告)日:2004-06-08

    申请号:US10235008

    申请日:2002-09-03

    IPC分类号: B23K1018

    CPC分类号: B23K1/018 B23K2101/40

    摘要: A method and structure for a chip detach apparatus and method that limits the solder ball maximum shear rate and, more particularly, that delays the application of shear force until a minimum predefined temperature is reached. The chip detach apparatus and method can be applied to chips with high solder ball counts, chips with small solder ball sizes, and chips with weak surface strength. The chip detach apparatus and method measures and accounts for variability in the electronic module manufacturing and assembly.

    摘要翻译: 用于限制焊球最大剪切速率的切屑分离装置和方法的方法和结构,更具体地说,延迟剪切力的施加直到达到最小预定温度。 芯片分离装置和方法可以应用于具有高焊球计数的芯片,具有小焊球尺寸的芯片和具有弱表面强度的芯片。 芯片分离装置和方法测量并考虑了电子模块制造和组装中的变化。

    Method and apparatus to manufacture an electronic package with direct wiring pattern
    8.
    发明授权
    Method and apparatus to manufacture an electronic package with direct wiring pattern 失效
    制造具有直接布线图案的电子封装的方法和装置

    公开(公告)号:US06459039B1

    公开(公告)日:2002-10-01

    申请号:US09597906

    申请日:2000-06-19

    IPC分类号: H05K102

    摘要: An electronic package assembly for electrical interconnection between two electronic modules having differing conductive array parameters is disclosed. The electronic package assembly includes two electronic modules, providing between the two electronic modules an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer of the electronic package assembly, with the conductors including a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors of the interposer of the electronic package assembly. The first set of conductive arrays includes the same conductive array parameters as a first electronic module and the second set of conductive arrays includes the same conductive array parameters as a second electronic module.

    摘要翻译: 公开了一种用于具有不同导电阵列参数的两个电子模块之间的电互连的电子封装组件。 电子封装组件包括两个电子模块,在两个电子模块之间提供具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列,所述第二导电阵列和第一导电阵列具有不同的参数。 多个导体横穿电子封装组件的插入件的厚度,其中导体包括任选涂覆有电介质材料的导电材料,导体在第一导电阵列处具有第一端,在第二导电阵列处具有第二端 由此连接其中的第一和第二导电阵列的导体适于空间转换不同的参数以提供电互连。 导电矩阵围绕电子封装组件的插入件的导体。 第一组导电阵列包括与第一电子模块相同的导电阵列参数,第二组导电阵列包括与第二电子模块相同的导电阵列参数。