公开(公告)号：US20120138336A1

公开(公告)日：2012-06-07

申请号：US13091074

申请日：2011-04-20

申请人： Ryoichi WATANABE ,  Going Sik KIM ,  Chang Sup RYU

发明人： Ryoichi WATANABE ,  Going Sik KIM ,  Chang Sup RYU

IPC分类号： H05K1/02 ,  B05D5/12

CPC分类号： H05K3/107 ,  H01L2224/05557 ,  H05K3/108 ,  H05K3/381

摘要： Disclosed herein is a printed circuit board and a method of manufacturing the same, in which a circuit pattern one end of which is embedded in a trench and the other end of which protrudes from an insulating layer is formed, so that the circuit pattern is not easily separated from the insulating layer and the separation problems of the circuit pattern due to undercutting are solved. Also, the adhesion between the insulating layer and the circuit pattern is enhanced, more stably forming a fine circuit pattern. Even when a plating resist is formed thin, it is possible to form the circuit pattern, resulting in a high-solution circuit pattern.

摘要翻译： 这里公开了一种印刷电路板及其制造方法，其中形成其一端嵌入沟槽中的电路图案，其另一端从绝缘层突出，使得电路图案不是 容易地与绝缘层分离，并且解决了由于底切引起的电路图案的分离问题。 此外，增强了绝缘层和电路图案之间的粘合性，更稳定地形成精细电路图案。 即使电镀抗蚀剂形成得较薄，也可形成电路图案，形成高溶液电路图形。

公开(公告)号：US20120168960A1

公开(公告)日：2012-07-05

申请号：US13340436

申请日：2011-12-29

申请人： Hye Jin KIM ,  Going Sik KIM ,  Chang Sup RYU

发明人： Hye Jin KIM ,  Going Sik KIM ,  Chang Sup RYU

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/45 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The preferred embodiment of the present invention can prevent signal distortions such as stress, or the like, occurring at the time of power delivery due to the difference in the lengths of the metal wires for electrically connecting each of the plurality of semiconductor chips formed on the dual die package substrate.

摘要翻译： 本发明的优选实施例可以防止由于用于电连接形成在多个半导体芯片上的多个半导体芯片中的每一个的金属线的长度差而在发电时发生的诸如应力等的信号失真 双模封装基板。

公开(公告)号：US20090152233A1

公开(公告)日：2009-06-18

申请号：US12367738

申请日：2009-02-09

申请人： Suk Hyeon CHO ,  Chang Sup RYU ,  Jin Soo JEONG ,  Jin Yong AHN

发明人： Suk Hyeon CHO ,  Chang Sup RYU ,  Jin Soo JEONG ,  Jin Yong AHN

IPC分类号： B44C1/22

CPC分类号： H05K1/183 ,  H01L2224/16225 ,  H05K3/062 ,  H05K3/064 ,  H05K3/244 ,  H05K3/28 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/10734 ,  H05K2203/1394 ,  Y10T29/4913 ,  Y10T29/49155

摘要： Disclosed is a printed circuit board (PCB) and a method of fabricating the same. A contact portion is formed on an internal layer of the multi-layered PCB. A groove is formed so as to expose the contact portion of the internal layer. A chip package is mounted on the PCB while being flip-chip bonded to the exposed contact portion of the internal layer.

摘要翻译： 公开了一种印刷电路板（PCB）及其制造方法。 接触部分形成在多层PCB的内层上。 形成凹槽以暴露内层的接触部分。 芯片封装安装在PCB上，同时倒装芯片结合到内层的暴露的接触部分。

公开(公告)号：US20110308069A1

公开(公告)日：2011-12-22

申请号：US13137669

申请日：2011-09-01

申请人： Eung Suek LEE ,  Je Gwang YOO ,  Chang Sup RYU ,  Jun Oh HWANG ,  Jun Heyoung PARK ,  Jee Soo MOK

发明人： Eung Suek LEE ,  Je Gwang YOO ,  Chang Sup RYU ,  Jun Oh HWANG ,  Jun Heyoung PARK ,  Jee Soo MOK

IPC分类号： H05K13/00 ,  C04B35/64

CPC分类号： H01L23/373 ,  B82Y30/00 ,  C04B35/80 ,  C04B2235/3217 ,  C04B2235/3418 ,  C04B2235/407 ,  C04B2235/408 ,  C04B2235/5288 ,  F28F3/02 ,  F28F21/02 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/3025 ,  Y10T29/49002 ,  Y10T29/4935 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing a cooling fin and package substrate that includes preparing a mold, which has a support base and a resin layer formed on the support base and including on a side thereof a groove, which is configured to form a cooling fin; printing fireable paste containing a carbon component on a side of the mold that has the groove configured to form a cooling fin; removing the support base to leave a cooling object; and firing the cooling object.

摘要翻译： 一种冷却翅片和封装基板的制造方法，其特征在于，包括：准备模具，所述模具具有支撑基体和树脂层，所述支撑基底和树脂层形成在所述支撑基部上，并且在其一侧包括凹槽，所述凹槽被构造成形成冷却翅片; 在所述模具的侧面上印刷含有碳成分的可燃性糊料，所述成型体具有形成冷却翅片的所述凹槽; 移除支撑底座以留下冷却物体; 并发射冷却对象。

公开(公告)号：US20120168220A1

公开(公告)日：2012-07-05

申请号：US13281264

申请日：2011-10-25

申请人： Han Ul Lee ,  Byung Bae SEO ,  Chang Sup RYU ,  Yong Sam LEE

发明人： Han Ul Lee ,  Byung Bae SEO ,  Chang Sup RYU ,  Yong Sam LEE

IPC分类号： H05K1/11 ,  H01K3/10

CPC分类号： H05K3/429 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/107 ,  H05K2203/1572 ,  Y10T29/49165

摘要： Disclosed herein are a multi-layer printed circuit board and a method of manufacturing the same. In the multi-layer printed circuit board and the method of manufacturing the same, circuit layers formed in a plurality of insulating layers are electrically interconnected through vias formed in a lump, thereby making it possible to secure bonding reliability of an interlayer circuit layer and more stably secure performance of the printed circuit board. In addition, since a stacked type via structure may be implemented by performing a via hole drilling process, a desmear process, and a copper plating process only one time after an insulating layer and an circuit layer are stacked, a manufacturing process, a manufacturing time, and manufacturing costs of the stacked type via structure may be reduced.

摘要翻译： 这里公开了多层印刷电路板及其制造方法。 在多层印刷电路板及其制造方法中，形成在多个绝缘层中的电路层通过一体形成的通孔电连接，从而可以确保层间电路层的结合可靠性和更多 稳定地确保印刷电路板的性能。 此外，由于堆叠型通孔结构可以通过在绝缘层和电路层堆叠后一次进行通孔钻孔工艺，去污工艺和镀铜处理来实现，制造工艺，制造时间 ，并且可以减小层叠型通孔结构的制造成本。

公开(公告)号：US20130175238A1

公开(公告)日：2013-07-11

申请号：US13474335

申请日：2012-05-17

申请人： Dae Jo HONG ,  Chang Bo LEE ,  Cheol Ho CHOI ,  Chang Sup RYU ,  Sung Pyo HONG ,  Jong Hoon JEON ,  Akira HOSOMI ,  Hiroshi TAKAMIYA

发明人： Dae Jo HONG ,  Chang Bo LEE ,  Cheol Ho CHOI ,  Chang Sup RYU ,  Sung Pyo HONG ,  Jong Hoon JEON ,  Akira HOSOMI ,  Hiroshi TAKAMIYA

IPC分类号： C09K13/06 ,  H05K3/00

CPC分类号： C09K13/06 ,  H05K3/067 ,  H05K3/383

摘要： This invention relates to an etching solution including hydrogen peroxide, sulfuric acid, chlorine ions, benzotriazole and pyrazole, and to a method of manufacturing a printed wiring substrate wherein the surface of the metal wiring of the printed wiring substrate is treated with an alkali solution, roughened using the etching solution and then subjected to anti-rust treatment, thus forming porous surface irregularities and micro anchors even with a small etching amount of the metal (Cu) to thereby obtain a high force of adhesion between the metal and an insulating material.

摘要翻译： 本发明涉及包括过氧化氢，硫酸，氯离子，苯并三唑和吡唑的蚀刻溶液，以及印刷线路基板的金属布线的表面用碱溶液处理的印刷布线基板的制造方法， 使用蚀刻溶液进行粗糙化，然后进行防锈处理，从而即使用小的蚀刻量的金属（Cu）也形成多孔表面凹凸和微锚，从而获得金属和绝缘材料之间的高粘合力。

公开(公告)号：US20130026626A1

公开(公告)日：2013-01-31

申请号：US13487926

申请日：2012-06-04

申请人： Cheol Ho CHOI ,  Chang Bo LEE ,  Chang Sup RYU

发明人： Cheol Ho CHOI ,  Chang Bo LEE ,  Chang Sup RYU

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K2203/041 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： Disclosed herein are a method for forming bumps and a substrate including the bumps. The method includes: coating a solder resist on a substrate and electrodes formed on the substrate: performing laser etching treatment on the solder resist to form openings for forming bumps; printing a composition for forming bumps in the openings for forming bumps; and performing a reflowing process.The present invention can decrease the number of processes and realize a fine bump pitch of 90 μm or less at the time of forming bumps. Further, the present invention can also decrease the number of times that alignment is performed, due to the decrease in the number of processes.

摘要翻译： 本文公开了一种用于形成凸块的方法和包括该凸块的基板。 该方法包括：在基板上形成阻焊剂和在基板上形成的电极：对阻焊剂进行激光蚀刻处理，形成用于形成凸块的开口; 在用于形成凸块的开口中印刷用于形成凸块的组合物; 并进行回流处理。 本发明可以减少处理次数，并且在形成凸块时实现90μm以下的微小凸点间距。 此外，由于处理次数的减少，本发明还可以减少对准的次数。

公开(公告)号：US20120043126A1

公开(公告)日：2012-02-23

申请号：US13213939

申请日：2011-08-19

申请人： Dae Jo HONG ,  Chang Sup RYU ,  Cheol Ho CHOI

发明人： Dae Jo HONG ,  Chang Sup RYU ,  Cheol Ho CHOI

IPC分类号： H05K1/02 ,  H05K1/00 ,  H05K3/00

CPC分类号： H05K3/305 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/3452 ,  Y02P70/613 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2924/014

摘要： Disclosed herein are a printed circuit board and a method of manufacturing the same, including: forming a protective layer on which a cover film is stacked on a base substrate; exposing the protective layer on which the cover film is stacked to photosensitize the protective layer and photodegrade the cover film; and developing the photodegraded cover film and the photosensitized protective layer to form an opening exposing a pad unit of a circuit layer which is an outermost layer of the base substrate on the protective layer, whereby the productivity of the printed circuit board can be improved without performing a process of separating a cover film.

摘要翻译： 这里公开了一种印刷电路板及其制造方法，包括：在基底基板上形成覆盖膜层叠的保护层; 使覆盖膜层叠的保护层曝光，对保护层进行光敏化，使遮盖膜光降解; 以及显影光降解的覆盖膜和光敏保护层，以形成在保护层上露出作为基底基板的最外层的电路层的焊盘单元的开口，由此可以提高印刷电路板的生产率，而不执行 分离覆盖膜的过程。