Intelligent PHY with security detection for ethernet networks
    1.
    发明授权
    Intelligent PHY with security detection for ethernet networks 有权
    智能PHY与以太网网络的安全检测

    公开(公告)号:US08839405B2

    公开(公告)日:2014-09-16

    申请号:US13571870

    申请日:2012-08-10

    IPC分类号: H04L29/06

    摘要: A physical layer device includes memory, a memory control module, and a physical layer module. The memory control module is configured to control access to the memory. The physical layer module is configured to store packets in the memory via the memory control module. The physical layer module includes an interface configured to receive the packets from a network device via a network and an interface bus. The interface bus includes at least one of a control module and a regular expression module. The at least one of the control module and the regular expression module is configured to inspect the packets to determine a security level of the packets. A network interface is configured to, based on the security level, provide the packets to a device separate from the physical layer device.

    摘要翻译: 物理层设备包括存储器,存储器控制模块和物理层模块。 存储器控制模块被配置为控制对存储器的访问。 物理层模块被配置为经由存储器控制模块将数据包存储在存储器中。 物理层模块包括经由网络和接口总线从网络设备接收分组的接口。 接口总线包括控制模块和正则表达式模块中的至少一个。 控制模块和正则表达模块中的至少一个被配置为检查分组以确定分组的安全级别。 网络接口被配置为基于安全级别将分组提供给与物理层设备分离的设备。

    Intelligent PHY with security detection for ethernet networks
    2.
    发明申请
    Intelligent PHY with security detection for ethernet networks 有权
    智能PHY与以太网网络的安全检测

    公开(公告)号:US20130212670A1

    公开(公告)日:2013-08-15

    申请号:US13571870

    申请日:2012-08-10

    IPC分类号: H04L29/06

    摘要: A physical layer device includes memory, a memory control module, and a physical layer module. The memory control module is configured to control access to the memory. The physical layer module is configured to store packets in the memory via the memory control module. The physical layer module includes an interface configured to receive the packets from a network device via a network and an interface bus. The interface bus includes at least one of a control module and a regular expression module. The at least one of the control module and the regular expression module is configured to inspect the packets to determine a security level of the packets. A network interface is configured to, based on the security level, provide the packets to a device separate from the physical layer device.

    摘要翻译: 物理层设备包括存储器,存储器控制模块和物理层模块。 存储器控制模块被配置为控制对存储器的访问。 物理层模块被配置为经由存储器控制模块将数据包存储在存储器中。 物理层模块包括经由网络和接口总线从网络设备接收分组的接口。 接口总线包括控制模块和正则表达式模块中的至少一个。 控制模块和正则表达模块中的至少一个被配置为检查分组以确定分组的安全级别。 网络接口被配置为基于安全级别将分组提供给与物理层设备分离的设备。

    ULTRA LINEAR CLASS AB, RF AMPLIFIER TOPOLOGY

    公开(公告)号:US20240356499A1

    公开(公告)日:2024-10-24

    申请号:US18622565

    申请日:2024-03-29

    申请人: Sehat Sutardja

    发明人: Sehat Sutardja

    IPC分类号: H03F1/56 H03F3/24

    摘要: An amplifier system comprising an input matching network configured to receive an input signal from a signal source. The input matching network is configured to impedance match between the amplifier system and the signal source. An input transformer is configured to receive the impedance matched input signal and perform voltage step down and current step up. An amplifier is configured to receive and amplify an output signal from the input transformer to generate an amplified signal. A low winding ratio output transformer provides isolation between an antenna and amplifier. An output matching network is configured to impedance match to an antenna and provide voltage step up. The input transformer may have a ratio of 2N:N, such as 2:1 ratio. At least one center tap of the input transformer may connect to a bias voltage. The amplifier system may be configured for operation in the radio frequency band.

    HIGH SPEED RIPPLE ADDER
    4.
    发明公开

    公开(公告)号:US20240256222A1

    公开(公告)日:2024-08-01

    申请号:US18423214

    申请日:2024-01-25

    申请人: Sehat Sutardja

    发明人: Sehat Sutardja

    IPC分类号: G06F7/506 H03K19/00

    CPC分类号: G06F7/506 H03K19/00

    摘要: Apparatus and method to logically process signals representative of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level of the logical processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay. At least one of the bit-representative signals is inverted prior to the input registers or prior to processing by the logical processing stage. The delay is reduced by omitting an inverting function in a carry circuit associated with at least one logical processing stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval.

    TRANSFORMER STRUCTURE
    5.
    发明公开

    公开(公告)号:US20230154674A1

    公开(公告)日:2023-05-18

    申请号:US17974434

    申请日:2022-10-26

    申请人: Sehat Sutardja

    发明人: Sehat Sutardja

    摘要: A transformer comprising a primary winding and a secondary winding. The primary winding has N2 number turns and having a first terminal and a second terminal. The secondary winding has having N1 fractional portions, which together form a full turn, are in close proximity to the primary winding to establish coupling between the primary winding and the N1 fractional coil portions, the transformer turn ratio from the primary winding to the secondary winding is N2:(N3/N1) where N2 is an integer equal to or greater than 1, N1 is an integer greater than or equal to 2, and N3 is an integer greater than or equal to 1. Also disclosed is a stacked integrated transformer having a primary winding and secondary winding of which one or both have a waterfall structure and a portion of which functions as a ground connected shield between the secondary winding and the primary winding.

    GPS-based traffic monitoring system
    7.
    发明授权
    GPS-based traffic monitoring system 有权
    基于GPS的交通监控系统

    公开(公告)号:US09047765B2

    公开(公告)日:2015-06-02

    申请号:US11171563

    申请日:2005-06-30

    申请人: Sehat Sutardja

    发明人: Sehat Sutardja

    摘要: A traffic information system for a vehicle comprises a transmitter and a global positioning system (GPS) associated with the vehicle that selectively generates location and vector data. A control module receives the location and vector data and wirelessly transmits the location and vector data using the transmitter when the vehicle is traveling on a first set of predetermined roads and does not transmit the location and vector data when the vehicle is traveling on a second set of predetermined roads.

    摘要翻译: 用于车辆的交通信息系统包括与车辆相关联的发射机和全球定位系统(GPS),其选择性地生成位置和矢量数据。 当车辆在第一组预定道路上行驶时,控制模块接收位置和矢量数据并使用发射器无线地发送位置和矢量数据,并且当车辆在第二组上行驶时不传送位置和矢量数据 的预定道路。

    TRIAC dimming systems for solid-state loads
    9.
    发明授权
    TRIAC dimming systems for solid-state loads 有权
    用于固态负载的TRIAC调光系统

    公开(公告)号:US08847517B2

    公开(公告)日:2014-09-30

    申请号:US13525711

    申请日:2012-06-18

    IPC分类号: H05B37/02 H05B33/08

    摘要: A system includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a switching circuit. The second coil is configured to generate a first current based on the first voltage to power a solid-state load. The system also includes a third coil. The third coil is configured to generate a second voltage based on the first voltage.

    摘要翻译: 一个系统包括一个变压器。 变压器包括第一线圈和第二线圈。 第一线圈被配置为基于开关电路的输出接收第一电压。 第二线圈被配置为基于第一电压产生第一电流以对固态负载供电。 该系统还包括第三线圈。 第三线圈被配置为基于第一电压产生第二电压。