公开(公告)号：US09515133B2

公开(公告)日：2016-12-06

申请号：US14539896

申请日：2014-11-12

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Herb He Huang ,  Hongtao Ge ,  Haiting Li

IPC分类号： H01L21/768 ,  H01L49/02 ,  H01L27/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522

CPC分类号： H01L28/10 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/768 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/535 ,  H01L27/0617 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.

摘要翻译： 公开了一种半导体器件及其制造方法。 该半导体器件包括设置在金属间介电层的表面上的电感器，该电感器不存在虚拟互连部件。 因此，寄生电容被减小或消除，并且电感器的Q值高。

公开(公告)号：US09362331B2

公开(公告)日：2016-06-07

申请号：US14242841

申请日：2014-04-01

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Herb He Huang ,  Mieno Fumitake

IPC分类号： H01L31/18 ,  H01L31/0232 ,  H01L27/146

CPC分类号： H01L27/14685 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14687

摘要： A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures.

摘要翻译： 一种用于形成图像传感器的方法包括提供衬底和形成多个光电二极管区域，每个光电二极管区域被空间地设置在衬底上。 该方法还包括形成覆盖多个光电二极管区域的层间电介质层，形成覆盖在层间电介质层上的屏蔽层，以及涂覆覆盖屏蔽层的二氧化硅轴承材料。 该方法还包括蚀刻二氧化硅载体材料的部分以形成多个第一透镜结构，并且继续形成多个第一透镜结构中的每一个以提供多个成品透镜结构。

公开(公告)号：US09349748B2

公开(公告)日：2016-05-24

申请号：US14564081

申请日：2014-12-08

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Herb He Huang ,  Haiting Li ,  Xingcheng Jin ,  Xinxue Wang ,  Hongbo Zhao ,  Fucheng Chen ,  Yanghui Xiang

IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4975

摘要： A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

摘要翻译： 半导体器件包括具有第一半导体衬底，掩埋绝缘层和形成在第一区域中的第二半导体衬底和设置在第二区域中的深沟槽隔离的堆叠的绝缘体上硅（SOI）衬底。 形成半导体器件的方法包括提供分别形成在第二半导体衬底内和第二半导体衬底上的浅沟槽隔离（STI）和晶体管的SOI衬底。 该方法还包括在第一区域上形成硬掩模，并使用硬掩模作为掩模去除第二区域中的STI，晶体管，第二半导体衬底和埋入绝缘层，并且形成覆盖深沟槽的覆盖层 隔离和包括晶体管的第二半导体衬底。

公开(公告)号：US11601106B2

公开(公告)日：2023-03-07

申请号：US16868373

申请日：2020-05-06

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION

发明人： Herb He Huang ,  Clifford Ian Drowley ,  Jiguang Zhu ,  Halting Li

IPC分类号： H03H3/02 ,  H03H9/17 ,  H03H9/05 ,  H03H9/58 ,  H03H9/10 ,  H01L27/20 ,  H03H3/007 ,  H03H9/02 ,  H03H9/15

摘要： A thin-film bulk acoustic resonator (FBAR) apparatus includes a lower dielectric layer including a first cavity; an upper dielectric layer including a second cavity, wherein the upper dielectric layer is on the lower dielectric layer; and an acoustic resonance film that is positioned between and separating the first and the second cavities. The acoustic resonance film includes a lower electrode layer, an upper electrode layer, and a piezoelectric film that is sandwiched between the lower and upper electrode layers. A plan view of the first and the second cavities overlap to form an overlapped region having a polygonal shape without parallel sides.

公开(公告)号：US10700663B2

公开(公告)日：2020-06-30

申请号：US15453728

申请日：2017-03-08

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION

发明人： Herb He Huang ,  Clifford Ian Drowley ,  Jiguang Zhu ,  Haiting Li

IPC分类号： H03H9/17 ,  H01L41/09 ,  H01P7/06 ,  H03H9/56 ,  H03H9/10 ,  H03H3/02

摘要： A resonator may include a first dielectric member, a second dielectric member, and a composite member. The first dielectric member may have a first cavity. The composite member may include a piezoelectric layer and may overlap at least one of the first dielectric member and the second dielectric member. At least one of the second dielectric member and the composite member may have a second cavity. The piezoelectric layer may be positioned between the first cavity and the second cavity. A projection of the first cavity in a direction perpendicular to a flat side of the first dielectric member and a projection of the second cavity in the direction may intersect each other to form a polygon. No two edges of the polygon may be parallel to each other.

公开(公告)号：US10433435B2

公开(公告)日：2019-10-01

申请号：US15261471

申请日：2016-09-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION

发明人： Herb He Huang ,  Clifford Ian Drowley ,  Hai Ting Li

IPC分类号： H01L21/768 ,  H05K3/46 ,  H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/58

摘要： A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole.

公开(公告)号：US09953877B2

公开(公告)日：2018-04-24

申请号：US14996091

申请日：2016-01-14

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Herb He Huang ,  Haiting Li ,  Jiguang Zhu ,  Clifford Ian Drowley

IPC分类号： H01L21/8234 ,  H01L21/306 ,  H01L21/304 ,  H01L21/265 ,  H01L21/683 ,  H01L21/762 ,  H01L23/48 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/31133 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate; forming a first dielectric cap layer covering the first surface of the first substrate; forming a first interconnect structure on the first dielectric cap layer; providing a carrier substrate; bonding the carrier substrate to the first substrate through the first dielectric cap layer; and from a second surface of the first substrate opposite to the first surface, thinning the first substrate to a second depth.

公开(公告)号：US09711502B2

公开(公告)日：2017-07-18

申请号：US15345135

申请日：2016-11-07

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Herb He Huang ,  Cliff Drowley

IPC分类号： H01L21/762 ,  H01L27/06 ,  B81C1/00 ,  H01L23/48 ,  B81B7/00 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L27/12 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522

CPC分类号： H01L27/0694 ,  B81B7/0006 ,  B81B2207/015 ,  B81C1/00333 ,  B81C2203/0118 ,  B81C2203/0735 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/10 ,  H01L28/40 ,  H01L29/66681 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, at least one first trench extending into the first semiconductor substrate from the first surface and having a first depth, at least one second trench extending into the first semiconductor substrate from the first surface and having a second depth greater than the first depth, a thinned semiconductor region with a first recessed region extending in the first semiconductor substrate from the second surface and having a first thickness, a second recessed region in the first semiconductor substrate extending from the second surface to the first surface, and a bulk dielectric layer covering the second surface of the first semiconductor substrate.

公开(公告)号：US09331069B2

公开(公告)日：2016-05-03

申请号：US14826184

申请日：2015-08-13

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Herb He Huang

IPC分类号： H01L27/06 ,  H01L45/00 ,  H01L27/11 ,  H01L45/02 ,  H01L27/24 ,  H01L29/45 ,  H01L29/49 ,  H01L29/08 ,  H01L27/10 ,  H01L21/768 ,  H01L21/265 ,  H01L29/417 ,  H01L27/22

CPC分类号： H01L27/0694 ,  H01L21/26533 ,  H01L21/76898 ,  H01L27/101 ,  H01L27/1112 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/4975 ,  H01L45/02 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608

摘要： A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit.

公开(公告)号：US09293472B2

公开(公告)日：2016-03-22

申请号：US14495884

申请日：2014-09-24

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Herb He Huang ,  Zhongshan Hong

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L23/552 ,  H01L21/76232 ,  H01L21/76289 ,  H01L21/84 ,  H01L23/66 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/7838 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.

摘要翻译： 集成电路包括具有第一半导体衬底，第一半导体衬底上的绝缘层和绝缘层上的第二半导体衬底的化合物半导体衬底，设置在第二半导体衬底上并具有被绝缘层绝缘的底部的晶体管 ，设置在晶体管的相对侧上的多个浅沟槽隔离件，设置在晶体管底部下方的空腔以及设置在空腔的相对侧上的多个隔离插塞。 通过具有位于晶体管下方的空腔，晶体管和衬底之间的寄生耦合减小，并且集成电路的性能得到改善。